Clock-independent latch setup-and-hold time in a combined D-type

Details Clock-independent latch setup-and-hold time in a combined D-type Clock-independent latch setup-and-hold time in a combined D-type

1998-12-07

2000-08-01

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, H03K 3356

Patent

active

060972300

ABSTRACT:
A combined D-type latch and D-type flip-flop circuit where the latch setup-and-hold time is independent of the clock state. This is accomplished in one method by rerouting the data path to the Master to provide equivalent delays to both the Master and the Slave. In a second method, a clocking circuit provides on-board clocking where the data ia always latched first into the Slave, and after a fixed delay, the data are latched into the Master.

REFERENCES:
patent: 5081377 (1992-01-01), Freyman
patent: 5656962 (1997-08-01), Banik
patent: 5905393 (1999-05-01), Rinderknecht et al.

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