Clocked-scan flip-flop for multi-threshold voltage CMOS circuit

Details Clocked-scan flip-flop for multi-threshold voltage CMOS circuit Clocked-scan flip-flop for multi-threshold voltage CMOS circuit

2005-03-01

2005-03-01

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S197000

Reexamination Certificate

active

06861887

ABSTRACT:
A clocked-scan flip-flop for multi-threshold CMOS (MTCMOS) is provided. The clocked-scan flip-flop includes a first switching unit which switches normal data that are input from the outside and outputs the data; a second switching unit which switches scan data that are input from the outside and outputs the data; a latch unit which latches the data input from the first switching unit or the second switching unit; and a clock input unit which controls the switching operations of the first and second switching units according to the result of a predetermined operation on a clock signal and a scan clock signal that are input from the outside. The clocked-scan flip-flop has the characteristics of a complementary pass-transistor (CP) flip-flop, that is, low power consumption and high performance. Also, the clocked-scan flip-flop provides a full-scale scan function for test purposes.

REFERENCES:
patent: 5717700 (1998-02-01), Crouch et al.
patent: 5719878 (1998-02-01), Yu et al.
patent: 6492854 (2002-12-01), Ku et al.
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Shin'ichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, Hideki Fukuda, Takao Kaneko, and Junzo Yamada, “A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone Application,” Nov., 1996, vol. 31, No. 11, pp. 1795-1802.

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