Reduced-latency floating-point pipeline using normalization shif
Reduced-width low-error multiplier
Reducing peak spectral error in inverse Fast Fourier Transform u
Reducing the hardware cost of a bank of multipliers by combining
Reduction of add-pipe logic by operand offset shift
Reduction of digital filter delay
Reduction of execution times for convolution operations
Reduction of periodic signals in pseudo-random noise...
Redundancy-free circuits for zero counters
Refinement of interpolated signals
Reflection filter
Reforming process having a high selectivity and activity for deh
Relaxed remainder constraints with comparison rounding
Reloadable floating point unit
Remainder calculating method, modular-multiplication method,...
Repetitive controller to compensate for odd harmonics
Reporting a saturated counter value
Reporting a saturated counter value
Representation of data transformation processes for...
Resampling method and resampler circuit