Relaxed remainder constraints with comparison rounding

Details Relaxed remainder constraints with comparison rounding Relaxed remainder constraints with comparison rounding

2011-08-23

2011-08-23

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S551000

Reexamination Certificate

active

08005884

ABSTRACT:
A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the division operation, the constraints for the remainder may be relaxed in order to reduce the area for look-up tables. An extra internal precision bit may not be used. Only one quotient may be calculated, rather than two, further reducing needed hardware to perform the rounding. Comparison logic may be required that may add a couple of cycles to the rounding computation beyond the calculation of the remainder. However, the extra latency is much smaller than a second floating-point multiply accumulate latency.

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“A Comparison of Three Rounding Algorithms for IEEE Floating-Pointmultiplication”; Even, et al.; This paper appears in Computer Arithmetic, 1999. Proceedings, 14th IEEE Symposium, pp. 225-232.

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