Parallel execution processor and instruction assigning...

Parallel execution processor and instruction assigning...

Planar cache layout and instruction stream therefor

Process for executing highly efficient VLIW

Processing apparatus including dedicated issue slot for...

Processing apparatus, processing method and compiler

Processor and a method for handling and encoding...

Processor and method for generating and storing compressed...

Processor and method for generating and storing compressed...

Processor executing SIMD instructions

Processor for executing highly efficient VLIW

Processor for executing highly efficient VLIW

Processor for VLIW instruction

Processor instruction including option bits encoding which...

Processor multiple function units executing cycle specifying...

Processor utilizing a template field for encoding instruction se

Read crossbar elimination in a VLIW processor

Register file indexing methods and apparatus for providing...

Replacing VLIW operation with equivalent operation requiring...

Resuming normal execution by restoring without refetching instru