Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2000-06-20
2002-05-28
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S213000, C712S210000, C712S211000, C712S212000, C712S023000, C712S208000, C712S209000, C712S215000
Reexamination Certificate
active
06397319
ABSTRACT:
BACKGROUND OF THE INVENTION
(1). Field of the Invention
The present invention relates to a processor with VLIW (Very Long Instruction Word) architecture, and in particular to a processor that executes instructions with comparatively short word length and high code efficiency.
(2). Description of the Prior Art
With the increase in demand for multimedia devices and the miniaturization of electronic circuits in recent years, there has been a growing need for microprocessors that can process multimedia data, such as audio data and image data, at high speed. One kind of processors that are capable of meeting this need are processors that use VLIW architecture, these being hereinafter referred to as “VLIW processors”.
VLIW processors include a number of internal operation units and so are able to simultaneously execute a number of operations in one VLIW in parallel. Such VLIW are generated by a compiler that investigates the extent to which parallel processing is possible at the source program level and performs scheduling. For embedded microprocessors used in consumer appliances, however, it is important to suppress the code size of programs, so that 256-bit VLIW, with their high incidence of no-operation instructions (hereinafter referred to as “NOP instructions”) and resulting poor code efficiency, are far from ideal.
One example of a VLIW processor that executes instructions with relative short word length is Japanese Laid-Open Patent Application H09-26878. This technique teaches a data processing apparatus that is a VLIW processor for executing 32-bit instructions that can simultaneously indicate a maximum of two operations.
FIGS. 1A and 1B
show the instruction format of the stated technique, with
FIG. 1A
showing the instruction format for simultaneously indicating two operations and
FIG. 1B
showing the instruction format for indicating only one operation. This technique aims to improve code efficiency by including a 2-bit value in the format field
410
that shows the number of operations in each instruction and the execution order.
The indication of a maximum of two operations by a single 32-bit instruction, however, does not achieve a sufficient degree of parallelism. There is also the problem of decreases in code efficiency of instructions when performing an operation using a constant that exceeds a given word length. As one example, when a 32-bit constant is split into an upper 16 bits and a lower 16 bits so that it can be set into registers, two 32-bit instructions are required just to indicate an operation using this constant.
SUMMARY OF THE INVENTION
In view of the stated problems, it is a first object of the present invention to provide a VLIW processor that executes instructions of comparatively short word length, but which have a high degree of parallelism and a highly efficient code structure so that several operations can be simultaneously indicated. As one example, three or more operations can be indicated by a single 32-bit instruction.
It is a second object of the present invention to provide a VLIW processor for executing instructions of a comparatively short word length that have a structure whereby the overall code efficiency will be comparatively unaffected even when handling constants of comparatively long word length.
The first object can be realized by a VLIW (Very Long Instruction Word) processor that decodes and executes an instruction that has at least two operation fields, of which a first operation field can only include one operation code for specifying an operation type and a second operation field includes a combination of one operation code and at least one operand used in an operation indicated by the second operation field, the VLIW processor including: a first decoding unit for decoding the operation code in the first operation field; a first execution unit for executing an operation indicated by the operation code in the first operation field in accordance with a decoding result of the first decoding unit; a second decoding unit for decoding the operation code in the second operation field; and a second execution unit for executing the operation indicated by the operation code in the second operation field on data which is indicated by the operands in the second operation field, in accordance with a decoding result of the second decoding unit.
By doing so, since at least one operation in the instruction can be indicated by merely inserting an operation code without an explicit indication of an operand, the word length of instructions can be reduced. As a result, a VLIW processor that executes instructions of comparatively short word length, but which have a highly efficient code structure so that several operations can be simultaneously indicated is achieved.
Here, a number of bits occupied by the operation code in the first operation field may be equal to a number of bits occupied by the operation code in the second operation field.
As a result, all operation codes that are included in an instruction will be composed of the same number of bits, which simplifies components such as the decoder circuits.
Here, the instruction may include three operation fields, wherein a third operation field in the three operation fields may occupy a same number of bits as the second operation field and may include a combination of one operation code and at least one operand, the VLIW processor further including: a third decoding unit which decodes, when an operation code is present in the third operation field, the operation code in the third operation field; and a third executing unit for executing an operation indicated by the operation code in the third operation field on data which is indicated by the operands in the third operation field, in accordance with a decoding result of the third decoding unit.
As a result, a VLIW processor with a high degree of parallelism whereby three operations can be simultaneously performed can be achieved.
Here, the first executing unit may control a control flow of a program including the instruction.
As a result, branch operations which do not normally require a large number of bits can be assigned to a short operation field. This means an instruction set with high code efficiency can be defined.
Here, the second executing unit may control transfer of the data that is indicated by the operands included in the second operation field, and the third executing unit may control executes an arithmetic logic operation on the data that is indicated by the operands included in the third operation field.
As a result, data transfer to and from an external memory can be indicated by a single operation in an instruction, so that the operand access circuit that should be provided in a VLIW processor can be simplified.
The second object of the present invention can be achieved by a VLIW processor that decodes and executes an instruction that has at least two operation fields, of which a first operation field can only include one of (i) a single operation code for specifying an operation type and (ii) a constant, and a second operation field includes one of (i) a combination of one operation code and at least one operand used in an operation indicated by the second operation field and (ii) a constant, the VLIW processor including: a first decoding unit which decodes, when an operation code is present in the first operation field, the operation code in the first operation field; a first executing unit for executing an operation indicated by the operation code in the first operation field, in accordance with a decoding result of the first decoding unit; a second decoding unit which decodes, when an operation code is present in the second operation field, the operation code in the second operation field; and a second executing unit for executing an operation indicated by the operation code in the second operation field on data which is indicated by the operands in the second operation field, in accordance with a decoding result of the second decoding unit.
With the stated construction, when it is necessary to put meaningless code int
Higaki Nobuo
Takayama Shuichi
Matsushita Electric Ind. Co., Ltd.
Pan Daniel H.
Price and Gess
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