Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Patent
1997-03-27
2000-03-28
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
712215, G06F 700
Patent
active
060444509
ABSTRACT:
Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.
REFERENCES:
patent: 5652878 (1997-07-01), Craft
patent: 5699536 (1997-12-01), Hopkins
patent: 5852741 (1998-12-01), Jacobs
The Study Report of Information Processing Society of Japan, vol. 93-ARC-102, pp. 17-24.
The Study Reports of Information Processing Society of Japan, vol. 94-ARC-107, pp. 113-120.
The Papers of Parallel Processing Symposium JSPP '92, pp. 265-272.
Ito Masanao
Nagashima Shigeo
Shimada Kentaro
Tamaki Yoshiko
Tanaka Yoshikazu
Coleman Eric
Hitachi , Ltd.
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