Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2003-08-08
2009-08-11
Ellis, Richard (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
Reexamination Certificate
active
07574583
ABSTRACT:
Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use of instructions that require large immediate data, while simultaneously maintaining an efficient encoding and decoding of instructions. The processing apparatus comprises a plurality of issue slots (UC0, UC1, UC2, UC3), wherein each issue slot comprises a plurality of functional units (FU20, FU21, FU22). The processing apparatus is arranged for processing data, based on control signals generated from a set of instructions being executed in parallel. The processing apparatus further comprises a dedicated issue slot (UC4) arranged for loading an immediate value (IMV1) in dependence upon a dedicated instruction (IMM). The immediate value (IMV1) can be stored in a dedicated register file (RF2) and the issue slot requiring this value can retrieve it from the dedicated register file (RF2).
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Leijten Jeroen Anton Johan
Mallon Willem Charles
Ellis Richard
Leydig , Voit & Mayer, Ltd.
Silicon Hive B.V.
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