Planar cache layout and instruction stream therefor

Details Planar cache layout and instruction stream therefor Planar cache layout and instruction stream therefor

1996-05-15

2000-10-10

An, Mang-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Long instruction word

712 27, 712208, 712200, 712210, 711100, 711125, 711202, 711211, G06F 1300

Patent

active

061311529

ABSTRACT:
Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.

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