Processor multiple function units executing cycle specifying...

Details Processor multiple function units executing cycle specifying... Processor multiple function units executing cycle specifying...

2006-04-04

2006-04-04

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing architecture

Long instruction word

C712S032000, C712S205000, C712S233000, C712S245000

Reexamination Certificate

active

07024538

ABSTRACT:
A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. Each function unit executes instructions according to machine cycles, each function unit executing one instruction per machine cycle. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.

REFERENCES:
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patent: 6393551 (2002-05-01), Singh et al.
patent: 0284364 (1988-09-01), None
patent: WO9629645 (1996-09-01), None
A Wolfe et al—“A Variable Instruction Stream Extension to the VLIW Architecture”—Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) Apr. 1991.

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