Rerouting VLIW instructions to accommodate execution units...

Details Rerouting VLIW instructions to accommodate execution units... Rerouting VLIW instructions to accommodate execution units...

2002-11-20

2008-12-30

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S024000

Reexamination Certificate

active

07472257

ABSTRACT:
Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers (120) are coupled to the plurality of execution units (160) via distribution means (140). Distribution means (140) have a plurality of dispatch units (144) coupled to the plurality of execution units (160) and a reroutable network, e.g. a data communication bus (142), coupling the plurality of execution units (120) to the plurality of dispatch units (144). The data communication bus (142) is controlled by control unit (148). Dispatch units (144) are arranged to detect dedicated instructions in the instruction flow, which signal the beginning of an inactive period of an execution unit (160a,160b,160c,160d) in the plurality of execution units (160). Subsequently, control unit (148) is notified, and the instruction flow from the plurality of registers (120) to the plurality of dispatch units (140) is rerouted as a result of the detection of the dedicated instruction.

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patent: 2002/0188828 (2002-12-01), Sugimoto

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