Massively parallel decoding and execution of variable-length...

Mechanism for extending the number of registers in a...

Mechanism for extending the number of registers in a...

Merging narrow register for resolution of data dependencies...

Method and apparatus for computing a packed absolute...

Method and apparatus for efficient loading and storing of...

Method and apparatus for generating a microinstruction responsiv

Method and apparatus for generating boundary markers for an...

Method and apparatus for identifying instruction boundaries

Method and apparatus for length decoding and identifying...

Method and apparatus for length decoding variable length...

Method and apparatus for processor code optimization using...

Method and apparatus for reducing encoding needs and ports...

Method and apparatus for representing variable-size computer...

Method and apparatus to extend the number of instruction...

Method and system for a two stage pipelined instruction...

Method and system for instruction length decode

Method for forming variable length instructions in a...

Method for forming variable length instructions in a...

Method for instructing a data processor to process data