Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Patent
1996-09-27
2000-03-21
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
712212, G06F 928
Patent
active
060414030
ABSTRACT:
A method and apparatus for decoding a macroinstruction, the macroinstruction including an operational code (opcode) and a specification of an operand, is described. The method includes two primary steps, which are performed either serially or in parallel. When performed serially, the steps may be performed in any order. The first primary step involves the generation of a first micro-instruction, specifying a first micro-operation, the first micro-instruction being derived from the specification of the operand of the macroinstruction. The second primary step involves the generation of a second micro-instruction, specifying a second micro-operation, the second micro-instruction being derived from the opcode of macroinstruction. The specification of the operand may specify the operand to be either a memory operand or a register operand in a manner that necessitates data processing or manipulation prior to a memory access or to execution of the second micro-instruction. More specifically, the specification of the operand in the macroinstruction may require alignment of operands retrieved from registers, prior to execution of the second instruction. In this case, the first micro-instruction may require a shift operation after retrieval of the operands.
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Boggs Darrell D.
Kyker Alan B.
Parker Donald D.
An Meng-Ai T.
Intel Corporation
Patel Gautam R.
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