Mechanism for extending the number of registers in a...

Details Mechanism for extending the number of registers in a... Mechanism for extending the number of registers in a...

2008-05-13

2008-05-13

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S218000

Reexamination Certificate

active

07373483

ABSTRACT:
An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies register address extensions, the register address extensions indicating the extended registers, where the extended registers cannot be specified by an existing instruction set, and where the existing instruction set includes the x86 instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set, and where the extended prefix tag includes opcode F1 (ICE BKPT) in the x86 instruction set. The extended register logic is coupled to the translation logic. The extended register logic receives the corresponding micro instructions, and for accesses the extended registers.

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