Method and apparatus for computing a packed absolute...

Details Method and apparatus for computing a packed absolute... Method and apparatus for computing a packed absolute...

1998-03-31

2001-06-05

Lee, Thomas (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S204000, C712S208000, C712S210000

Reexamination Certificate

active

06243803

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of microprocessors; more particularly, the present invention relates to a method and apparatus for computing a sum of absolute differences.
2. Description of Related Art
A sum of absolute differences is used in many applications including video applications such as Motion Pictures Expert Group (MPEG) encoding.
One method of computing a packed sum of absolute differences (PSAD) of packed data A having eight byte elements A
0
. . . A
7
and packed data B having eight byte elements B
0
. . . B
7
is to compute Ai−Bi and Bi−Ai for each value of i from 0 to 7, select the results that are non-negative, and add the non-negative results together. One implementation uses sixteen adders (two adders for each pair of byte elements), eight muxes (to select the non-negative values from each pair of results) and an adder tree to sum the non-negative results.
As more devices are used, more silicon area is needed in a semiconductor device. Semiconductor devices generally have a cost proportional to the silicon area used. Therefore, it is desirable to reduce the number of devices used to perform the PSAD instruction.
One method of computing a PSAD with less devices is to use the same device to serially operate on multiple data elements. For example, one adder may compute A
0
−B
0
and B
0
−A
0
sequentially, another may compute A
1
−B
1
and B
1
−A
1
sequentially, etc. This reduces the number of adders (silicon area) used, but increases the amount of time required to compute a PSAD.
What is needed is a method and apparatus to reduce the amount of silicon area required to implement a PSAD instruction without increasing the time required to compute the PSAD.
SUMMARY OF THE INVENTION
A method and apparatus for computing a Packed Absolute Differences is described. According to one such method and apparatus, a third packed data having a third plurality of elements and the plurality of sign bits is produced, each of the third plurality of elements and the plurality of sign bits being computed by subtracting one of a first plurality of elements of a first packed data from a corresponding one of a second plurality of elements of a second packed data. The third plurality of elements and the plurality of sign bits are stored. A fourth packed data having a fourth plurality of elements is produced, each of the fourth plurality of elements being computed by subtracting one of the third plurality of elements from the corresponding one of an at least one element, if the corresponding one of a plurality of sign bits is in a first state; and adding one of the third plurality of elements from the corresponding one of the at least one element, if the corresponding one of the plurality of sign bits is in a second state.


REFERENCES:
patent: 5001662 (1991-03-01), Baum
patent: 5606677 (1997-02-01), Balmer et al.
patent: 5712797 (1998-01-01), Descales et al.
patent: 5719642 (1998-02-01), Lee
patent: 5721697 (1998-02-01), Lee
patent: 5724032 (1998-03-01), Klein et al.
patent: 5734420 (1998-03-01), Lee et al.
patent: 5737537 (1998-04-01), Gardos et al.
patent: 5740037 (1998-04-01), McCann et al.
patent: 5742529 (1998-04-01), Mennemeier et al.
patent: 5760961 (1998-06-01), Tompkin et al.
patent: 5763883 (1998-06-01), Descales et al.
patent: 5787210 (1998-07-01), Kim
patent: 5790208 (1998-08-01), Kwak et al.
patent: 5793879 (1998-08-01), Benn et al.
patent: 5793900 (1998-08-01), Nourbakhsh et al.
patent: 5818739 (1998-10-01), Peleg et al.
patent: 5835389 (1998-11-01), Wong
patent: 5835782 (1998-11-01), Lin et al.
patent: 5841676 (1998-11-01), Ali et al.
patent: 5852473 (1998-12-01), Horne et al.
patent: 5865752 (1999-02-01), Seyed-Bolorforosh et al.
patent: 5876342 (1999-03-01), Chen et al.
patent: 5880979 (1999-03-01), Mennemeier et al.
patent: 5884089 (1999-03-01), Orian et al.
patent: 5901248 (1999-05-01), Fandrianto et al.
patent: 5909552 (1999-06-01), Jensn et al.
patent: 5935863 (1999-08-01), Descales et al.
patent: 5944771 (1999-08-01), Shiraishi
patent: 5946405 (1999-08-01), Kim et al.
patent: 5953240 (1999-09-01), Prabhu et al.
patent: 5960193 (1999-09-01), Guttag et al.
patent: 6026483 (2000-02-01), Oberman et al.
patent: 6032170 (2000-02-01), Guttag et al.
patent: 6036350 (2000-03-01), Mennemeier et al.
patent: 6070237 (2000-05-01), Peleg et al.
Visual Instruction Set (VIS™), User's Guide, Sun Microsystems, Inc., version 1.1 Mar., 1997, pp. 41-43, 87-88.

Affiliated with

Also associated with

Rating

Method and apparatus for computing a packed absolute... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for computing a packed absolute..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for computing a packed absolute... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2520014