Method and apparatus for efficient loading and storing of...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S002000

Reexamination Certificate

active

07581084

ABSTRACT:
A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.

REFERENCES:
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4541046 (1985-09-01), Nagashima et al.
patent: 4644471 (1987-02-01), Kojima et al.
patent: 4677573 (1987-06-01), Brown et al.
patent: RE32493 (1987-09-01), Matsumoto et al.
patent: 4785400 (1988-11-01), Kojima et al.
patent: 4841438 (1989-06-01), Yoshida et al.
patent: 4881168 (1989-11-01), Inagami et al.
patent: 4994962 (1991-02-01), Mageau et al.
patent: 5073970 (1991-12-01), Aoyama et al.
patent: 5155820 (1992-10-01), Gibson
patent: 5201058 (1993-04-01), Kinoshita et al.
patent: 5226171 (1993-07-01), Hall et al.
patent: 5241633 (1993-08-01), Nishi
patent: 5261113 (1993-11-01), Jouppi
patent: 5299320 (1994-03-01), Aono et al.
patent: 5349692 (1994-09-01), Nishi
patent: 5418973 (1995-05-01), Ellis et al.
patent: 5423051 (1995-06-01), Fuller et al.
patent: 5481746 (1996-01-01), Schiffleger et al.
patent: 5510934 (1996-04-01), Brennan et al.
patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5535347 (1996-07-01), Grochowski et al.
patent: 5537538 (1996-07-01), Bratt et al.
patent: 5537606 (1996-07-01), Byrne
patent: 5544337 (1996-08-01), Beard et al.
patent: 5561808 (1996-10-01), Kuma et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5574924 (1996-11-01), Yoshinaga et al.
patent: 5586276 (1996-12-01), Grochowski et al.
patent: 5604909 (1997-02-01), Joshi et al.
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5638500 (1997-06-01), Donovan et al.
patent: 5669013 (1997-09-01), Watanabe et al.
patent: 5673407 (1997-09-01), Poland et al.
patent: 5689653 (1997-11-01), Karp et al.
patent: 5734874 (1998-03-01), Van Hook et al.
patent: 5740402 (1998-04-01), Bratt et al.
patent: 5742277 (1998-04-01), Gossett et al.
patent: 5812147 (1998-09-01), Van Hook et al.
patent: 5832288 (1998-11-01), Wong
patent: 5848286 (1998-12-01), Schiffleger et al.
patent: 5864703 (1999-01-01), Van Hook et al.
patent: 5887183 (1999-03-01), Agarwal et al.
patent: 5898882 (1999-04-01), Kahle et al.
patent: 5931945 (1999-08-01), Yung et al.
patent: 5933157 (1999-08-01), Van Hook et al.
patent: 5933650 (1999-08-01), Van Hook et al.
patent: 5938756 (1999-08-01), Van Hook et al.
patent: 5946496 (1999-08-01), Sugumar et al.
patent: 5954815 (1999-09-01), Joshi et al.
patent: 5982939 (1999-11-01), Van Hook
patent: 6006315 (1999-12-01), Park
patent: 6058465 (2000-05-01), Nguyen
patent: 6075906 (2000-06-01), Fenwick et al.
patent: 6098162 (2000-08-01), Schiffleger et al.
patent: 6141673 (2000-10-01), Thayer et al.
patent: 6166748 (2000-12-01), Van Hook et al.
patent: 6167507 (2000-12-01), Mahalingaiah et al.
patent: 6304963 (2001-10-01), Elwood
patent: 489552 (1992-06-01), None
Motorola Inc., “PowerPC Microprocessor Family: The Programming Environments”, 1994.
IBM, “PowerPC 740 and PowerPC 750 RISC Microprocessor Family User Manual”, 1998.
MIPS Technologies, Inc., Silicon Graphics Introduces Enhanced MIPS® Architecture to Lead the Interactive Digital Revolution—Future Digital Media Processors Will Enable New World of High-Performance and Low-Cost Interactive Digital Applications, 1996.
Web Extension I: Survey of RISC Architectures.
MIPS V Instruction Set.
MIPS Extension for Digital Media with 3D.
IEEE, “Subword Parallelism With MAX-2”, 1996.
Web Extension I: Survey of RISC Architectures, 1997.
MIPS V Instruction Set, 1996.
MIPS Extension for Digital Media with 3D, 1996.
IBM. PowerPC™ Microprocessor Family: The Programming Environments for 32-Bit Microprocessors. Hopewell Junction, NY: IBM Corporation © Feb. 21, 2000, pp. 4-28 to 4-41.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for efficient loading and storing of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for efficient loading and storing of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for efficient loading and storing of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4105870

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.