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Configurable pipeline to process an operation at alternate...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate

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Context switching pipelined microprocessor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Continued processing of out-of-order non-architectual operations

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Control bit vector storage for a microprocessor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Control of processor pipeline movement through replay queue and

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Control word register renaming

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Controlling out of order execution pipelines issue tagging

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Controlling writes to non-renamed register space in an...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Counting instructions to skip in superscaler processor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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