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Line cache controller with lookahead

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Line fill techniques

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Line rate buffer using single ported memories for variable...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Line swapping scheme to reduce back invalidations in a snoop...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Linear address generator and method for generating a linear...

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
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Linear and non-linear object management

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
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Linear and non-linear object management

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
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Linear combiner weight memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Linear object management for a range of flash memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Linear object management for a range of flash memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Linear space allocation mechanisms in data space

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Linearly addressable microprocessor cache

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
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Linearly addressable microprocessor cache

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
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Linked list DMA descriptor architecture

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Linked list memory and method therefor

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Linked list traversal with reduced memory accesses

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Linked list traversal with reduced memory accesses

Electrical computers and digital processing systems: memory – Address formation – Hashing
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Linked-list early race resolution mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Linking method under mother and child block architecture for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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List based method and apparatus for selective and rapid...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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