Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
2000-02-21
2002-06-11
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S220000, C711S211000, C711S212000, C708S708000, C708S709000
Reexamination Certificate
active
06405298
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to circuitry within a processor for generating a linear address, and in specific to a parallel design of a linear address generator (LAGEN) that is capable of high-speed linear address generation.
BACKGROUND
A linear address generator (“LAGEN”) is typically implemented in processors of the prior art, such as the Merced processor developed by Intel Corporation in partnership with Hewlett Packard. An exemplary function of a LAGEN is to generate a memory address for data memory load in a processor to enable support for both IA-64 mode and x86 mode of operation, which are well-known modes of operation in the prior art. Prior art LAGENs typically require at least two clock cycles to complete (i.e., to generate a resulting linear address). An example of a typical LAGEN implementation of the prior art is illustrated in FIG.
1
. As shown in
FIG. 1
, LAGEN circuitry
100
is implemented within a processor, and such LAGEN circuitry
100
typically allows for both 32-bit mode operation and 16-bit mode operation. 32-bit mode operation utilizes a 32-bit memory address, while 16-bit mode operation utilizes a 16-bit memory address. For instance, 16-bit mode operation is commonly utilized to perform x86 instructions that are 16 bits. LAGEN circuitry
100
includes LATCHES
10
,
12
, and
14
, which latch operands IMM[
31
:
0
], SRC
1
[
31
:
0
], and SRC
2
[
31
:
0
], respectively. In
FIG. 1
, IMM[
31
:
0
] (i.e., “immediate address”), SRC
1
[
31
:
0
] (i.e., “source
1
”), and SRC
2
[
31
:
0
] (i.e., “source
2
”) represent input operands used to compute the memory address. LAGEN circuitry
100
further includes an adder, such as the 32-bit adder
16
, to add the first two operands, SRC
1
[
31
:
0
] and IMM[
31
:
0
] of FIG.
1
. Adder
16
produces a result having the higher 16 bits, shown as effective address (EA) EA[
31
:
16
], and the lower 16 bits, shown as EA[
15
:
0
], separated.
Thereafter, the higher 16 bits (i.e., bits EA[
31
:
16
]) are ANDed with a mode_
32
control bit in the AND gate
18
to obtain an intermediate result. When the mode_
32
control bit is set to 1 (high), the higher 16 bits EA[
31
:
16
] are passed as the output of AND gate
18
. That is, when 32-bit mode operation is enabled, the circuitry passes the higher 16 bits EA[
31
:
16
] through AND gate
18
where they are combined with the lower 16 bits EA[
15
:
0
] resulting in an intermediate result of {EA[
31
:
16
], EA[
15
:
0
]}. On the other hand, when 32-bit mode operation is disabled (meaning 16-bit mode is enabled), the mode_
32
control bit is set to 0. Accordingly, the output of AND gate
18
will be zero for each of the higher 16 bits. That is, AND gate
18
zeroes out all of the higher 16 bits and leaves the lower 16 bits EA[
15
:
0
] undisturbed, resulting in an intermediate result of {0
31
, 0
30
, 0
29
, . . . 0
16
, EA[
15
:
0
]}. It should be recognized that regardless of whether 32-bit mode or 16-bit mode is enabled, the lower 16 bits resulting from adder
16
, i.e., EA[
15
:
0
], are utilized for the intermediate result.
This intermediate result is then added with the operand SRC
2
[
31
:
0
], which has been latched in latch
14
. As shown in
FIG. 1
, adder
20
is used to add the intermediate result and SRC
2
[
31
:
0
] to generate a final result, i.e., the final linear address LA[
31
:
0
]. Thus, the prior art typically utilizes a 2-series, 32-bit addition implementation as described above in conjunction with FIG.
1
. That is, the prior art typically requires first adding the SRC
1
[
31
:
0
] and IMM[
31
:
0
] operands to obtain an intermediate result, and then the intermediate result is modified with AND gates for either 32-bit mode or 16-bit mode operation. Thereafter, a second addition is performed, in which the intermediate result is added to the SRC
2
[
31
:
0
] operand to generate the linear address.
Prior art LAGEN implementations are problematic because they require a relatively lengthy time to generate the final linear address LA[
31
:
0
]. For example, as shown in
FIG. 1
, such an implementation may require well over 800 picoseconds to obtain the final linear address LA[
31
:
0
]. For instance, in the exemplary prior art implementation illustrated in
FIG. 1
, latching the operands into latches
10
,
12
, and
14
requires approximately 150 picoseconds, executing adder
16
requires approximately 350 picoseconds, executing AND gate
18
requires approximately 150 picoseconds, and executing adder
20
requires approximately 350 picoseconds. Therefore, such prior art implementation requires a total time of approximately 1000 picoseconds (or 1 nanosecond) to generate a linear address LA[
31
:
0
]. With increasing clock speeds (i.e., processor speeds), it becomes impossible to generate a linear address in a timely manner utilizing a prior art implementation. For example, it becomes impossible to generate a linear address within a single clock cycle utilizing prior art LAGEN implementations. For instance, when operating at a 1 gigahertz (Ghz) clock speed (i.e., 10
9
cycles per second), the LAGEN must be capable of generating a linear address within 1000 picoseconds (1 nanosecond) in order to complete within a single clock cycle. Because network bypassing, as well as other tasks that are typically required, the LAGEN circuitry may be required to complete substantially faster than 1 nanosecond to generate a linear address within 1 clock cycle of a 1 GHz clock. An example of one task that may need to be performed, thereby requiring the LAGEN to complete very fast, is a check on the memory address limit to determine if the linear address is valid. Prior art LAGEN implementations are unable to achieve a result in such a timely manner.
It is very desirable to provide a single-cycle LAGEN to enable a much simpler design in the first level cache (i.e., L
0
cache), as well as a much simpler design for a 16-bit mode translator recorder IVE, which may be implemented within a processor. Generally, IVE is a major block of circuitry that enables 16-bit mode and 8-bit mode x86 instructions to be executed within IA-64 architecture processors, such as the Merced CPU from Hewlett-Packard Company. Prior art processors, such as Merced, typically include a two-cycle LAGEN and an out-of-order IVE. Generally, an out-of-order IVE is much more complex in design, consumes a larger amount of surface area (e.g., silicon), has increased routing congestion, and requires more effort to verify functional correctness and electrical reliability, than for an in-order IVE. Accordingly, it is desirable to have a single-cycle LAGEN to enable an in-order IVE for a processor. Furthermore, a single-cycle LAGEN would generally allow for faster accesses to the first-level cache. In general, a LAGEN generates linear addresses for all on-chip cache access, e.g., access to level
1
(“L
0
”), level
2
(“L
1
”), etc.). A single-cycle LAGEN would not only enable faster cache access, but would also facilitate a simpler cache structure. With a single-cycle LAGEN, an in-order IVE may be implemented, which is generally less complex and much smaller than an out-of-order IVE, which is typically required for prior art, two-cycle LAGENs.
SUMMARY OF THE INVENTION
In view of the above, a desire exists for a high-speed LAGEN for generating a linear address within a processor in a timely manner. A further desire exists for a high-speed LAGEN that is capable of generating a linear address in substantially less than 1 nanosecond. For instance, a desire exists for a high-speed LAGEN that is capable of generating a linear address in less than 0.5 nanosecond. Yet a further desire exists for a high-speed LAGEN that includes linear address generation and a bypass network, and is capable of generating a
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