Linked list DMA descriptor architecture

Details Linked list DMA descriptor architecture Linked list DMA descriptor architecture

1999-10-20

2004-08-24

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C710S022000, C710S033000, C711S154000

Reexamination Certificate

active

06782465

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to computer systems and direct memory access controllers in particular.
BACKGROUND OF THE INVENTION
In the early days of computers, data was moved in and out of memory by a central processing unit (CPU). However, as data transfer rates for mass storage devices such as hard drives or CD-ROMs increased, the CPU was too slow to handle the transfer of data and its use prevented the CPU from performing other tasks. As a result, most computers now incorporate direct memory access controllers (DMAs) to move data to and from a memory. A DMA operates by taking control of an address and data bus to either read data from or write data to a memory. To move data, a CPU gives the DMA controller an address of a DMA descriptor. The descriptor is a set of data that includes some predefined information including the size of a data block to be moved as well as a pointer with the address of the data block in memory.
In the past, each descriptor contained only one or exactly two data pointers. Each time the DMA controller was to move a data block, a new descriptor had to be read, thereby reducing the rate at which data could be moved. To speed data transfer rates, there is a need for a method of reducing the number of descriptors a DMA controller must read to move data.
SUMMARY OF THE INVENTION
To increase the rate at which data can be transferred by a DMA controller, a descriptor includes an address of a subsequent descriptor as well as an indication of a variable number of data pointers contained within the subsequent descriptor. The number of pointers in the subsequent descriptor is stored in the DMA controller. Upon reading a subsequent descriptor, the stored number of pointers controls a number of read cycles performed by the DMA controller.
In a presently preferred embodiment of the invention, the descriptors are stored in an aligned 32-bit memory. The last two address bits of the descriptor address are not needed and are therefore used to store the number of pointers in the next descriptor.
A DMA controller in accordance with the present invention includes a counter that stores a number of data pointers in a subsequent descriptor. Upon reading the descriptor, the counter controls a number of read cycles performed by the DMA controller when operating on the next descriptor.


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Promoters of the 1394 HCI: “1397-4 Open Host Controller Interface Specification,” Release 1.00, Oct. 20, 1997 Copyright 1996, 1997; pp. ii-xiv; 1-170.*
“DMA Controller Unit,” Intel Processor Developers Manual, last modified Mar. 26, 1999, section 19, pp. 19-1-19-5.

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