Linking method under mother and child block architecture for...

Details Linking method under mother and child block architecture for... Linking method under mother and child block architecture for...

2007-04-17

2007-04-17

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S156000

Reexamination Certificate

active

10733397

ABSTRACT:
A method of reducing the frequency of erasing steps of a flash memory is described. A linking method under a mother and a child block architecture for building a check area and a logic page of the child block in order to reduce the frequency of erasing steps of the flash memory so that the service life of the flash memory can be extended and also the processing speed can be promoted.

REFERENCES:
patent: 2002/0147882 (2002-10-01), Pua et al.

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