Linearly addressable microprocessor cache

Details Linearly addressable microprocessor cache Linearly addressable microprocessor cache

1997-01-08

1998-06-02

Harrity, John E.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

36424341, 3642565, 364DIG1, G06F 1210

Patent

active

057616914

ABSTRACT:
A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast translation to a logical address for operation with functional units of microprocessor. Also disclosed is a microprocessor which includes linear tag array and a physical tag array corresponding to the linear tag array, thus allowing the contents of a microprocessor cache to be advantageously monitored from an external bus without slowing the main instruction and data access processing paths.

REFERENCES:
patent: 5321836 (1994-06-01), Crawford et al.

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