Logical cache memory storing logical and physical address inform

Logical library architecture for data storage applications...

Logical storage of UDF descriptors by mapping a plurality of...

Logical unit number increasing device, and logical unit...

Logically partitioning different classes of TLB entries...

Lookaside buffer for address translation in a computer system

Machine-independent memory management system within a...

Maintaining processor resources during architectural events

Maintaining reverse mappings in a virtualized computer system

Maintaining shadow page tables in a sequestered memory region

Maintaining validity of cached address mappings

Maintenance of speculative state of parallel executed jobs...

Management of access to data from memory

Management of access to data from memory

Managing memory in a parallel processing environment

Mapper circuit with backup capability

Mapping a logical address to a plurality on non-logical...

Mapping an N -bit application ported from an M -bit...

Mapping data blocks to storage blocks to wrap around storage...

Mapping memory in a parallel processing environment