Architecture for decimation algorithm
Architecture for high sampling rate, high resolution analog-to-d
Architecture for high speed analog to digital converters
Architecture for inverse quantization and multichannel processin
Architecture for multi-stage decoding of a CABAC bitstream
Architecture for voltage scaling DAC
Architecture to reduce errors due to metastability in analog...
Area and power efficient analog to digital converter and...
Area efficient, sequential gray code to thermometer code...
Area integrator servo demodulator with on-chip CMOS analog-to-di
Area-efficient, digital variable resistor with high resolution
Arithmetic coding apparatus and image processing apparatus
Arithmetic coding context model that accelerates adaptation for
Arithmetic coding context model that adapts to the amount of dat
Arithmetic coding data compression/de-compression by selectively
Arithmetic coding/decoding apparatus of MQ-Coder system and...
Arithmetic compression coding using interpolation for ambiguous
Arithmetic decode without renormalization costs
Arithmetic decode without renormalization costs
Arithmetic decoding apparatus