Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-08-30
2001-04-24
Young, Brain (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
Reexamination Certificate
active
06222476
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an analog-to-digital converter. More specifically, an analog-to-digital converter having reduced metastability errors is disclosed.
2. Description of Related Art
Flash analog-to-digital converter (“ADC”) is often utilized in high-speed signal processing applications. Examples of such high-speed signal processing applications include hard disk drive (“HDD”) read channel, digital video, instrumentation, and telecommunication. One goal for analog-to-digital converters is low error rate. Typical flash ADC architecture employs comparators coupled to thermometer-to-binary encoding logic that output the binary code digital output. Thus, reducing comparator metastability errors in high-speed ADCs is critical for achieving low error rate in the final digital output of the ADCs.
Metastability error occurs when the difference at the two inputs of a comparator is small. The comparator circuit requires a relatively long period of time to produce a well-defined logic output when the input differential is relatively small. Generally, all comparators have a small input differential voltage range for which the output does not reach the full logic level, e.g., either a logic high (“1”) or a logic low (“0”), in a given clock period. Because the comparator is coupled to the downstream encoder of the ADC, the subsequent logic gates in the encoder may interpret the logic level output from the comparator at an incorrect level. Such incorrect interpretation of the comparator output often causes a gross error in the final binary code digital output.
One method for reducing metastability error is to improve the design of comparators. However, comparator requirements for low error rates often conflict with requirements for other performance metrics. Another method for reducing metastability error is to employ Gray encoding as an intermediate step to lower the probability of metastable states. However, employing the Gray encoding requires a relatively complex Gray-to-binary conversion between the thermometer and binary codes.
What is needed is a system and method to reducing metastability error in an ADC that is less complex, cost effective and easy to implement.
SUMMARY OF THE INVENTION
An ADC having reduced metastability errors is disclosed. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
The n-bit ADC having reduced errors due to metastability comprises a plurality of comparators each adapted to compare an analog input and one of a plurality of comparator reference voltages, the plurality of comparators are configured to output a thermometer code corresponding to the analog input and a thermometer-to-binary encoder for converting the thermometer code to a binary code digital output. The thermometer-to-binary encoder includes a transition detection logic adapted to detect a transition point in the thermometer code and to generate a transition codeword, the transition codeword having at least one transition bit corresponding to the transition point, an intermediate encoding logic adapted to encode the transition codeword into first intermediate signals, a converter logic adapted to convert the first intermediate signals into converted intermediate signals such that same converted intermediate signals result from first intermediate signals corresponding to a transition codeword having more than one transition bit and first intermediate signals corresponding to another transition codeword having one of the more than one transition bit, and a converted signals mapper for mapping the converted signals to the binary code digital output.
In another embodiment, the transition detection logic may include inverters and AND gates where a threshold voltage of each inverter is preferably greater than a threshold voltage of each corresponding AND gate to which the output of each inverter is input.
The method for converting a thermometer code to a binary code comprises generating a transition codeword according to a transition point in the thermometer code, the transition codeword having at least one transition bit corresponding to the transition point, encoding the transition codeword into first intermediate signals, converting the first intermediate signals into converted intermediate signals such that same converted intermediate signals result from first intermediate signals corresponding to a transition codeword having more than one transition bit and first intermediate signals corresponding to another transition codeword having one of the more than one transition bit, and mapping the converted signals to the binary code digital output.
These and other features and advantages of the present invention will be presented in more detail in the following detailed description and the accompanying figures, which illustrate by way of example the principles of the invention.
REFERENCES:
patent: 5382955 (1995-01-01), Knierim
patent: 5959564 (1999-09-01), Gross
Cideciyan, Roy D.; Dolivo, Francois; Hermann, Beto; Hirt, Walter, “A PRML System for Digital Magnetic Recording”, Jan. 1, 1992, IEEE Journal on Selected Areas in Communications.
Lee Sang-soo
Pan Tzu-Wang
LSI Logic Corporation
Young Brain
LandOfFree
Architecture to reduce errors due to metastability in analog... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Architecture to reduce errors due to metastability in analog..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture to reduce errors due to metastability in analog... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2517116