Architecture for high sampling rate, high resolution analog-to-d

Details Architecture for high sampling rate, high resolution analog-to-d Architecture for high sampling rate, high resolution analog-to-d

1988-11-22

1990-02-20

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

341161, 341155, H03M 120, H03M 138

Patent

active

049030264

ABSTRACT:
A high resolution analog-to-digital (A/D) converter (14) and a pipelined A/D converter are used in a single system so that unknown offset and gain errors of the pipe-lined A/D converter are determined and corrected. Each stage of the pipelined A/D converter includes a flash A/D converter (16), a corresponding digital-to-analog (D/A) converter (18), and a differential amplifier (20) so that, in each stage the output voltage of the D/A converter is subtracted from a sample of the analog input voltage, to constitute the input signal for the next stage. The flash A/D converter of each stage addresses digital words in memory (22) which, when summed by an adder chain (24), constitute the output signal of the system. The flash A/D converter output signals are also supplied to corresponding stages of a shift register (28 or 28') which accumulates the memory address bits. A comparator and finite state machine (26) receives the memory address bits from the shift register and iteratively compares the digital output signals of the pipelined A/D converter and the high resolution A/D converter and corrects the words in memory addressed by the flash A/D converters to improve resolution of the system.

REFERENCES:
patent: 3790947 (1974-02-01), Campbell et al.
patent: 4308524 (1981-12-01), Harrison et al.
patent: 4768016 (1988-08-01), Chu et al.

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