Architecture for voltage scaling DAC

Details Architecture for voltage scaling DAC Architecture for voltage scaling DAC

2000-06-22

2002-07-02

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S154000

Reexamination Certificate

active

06414616

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to digital-to-analog converters (DACs) and in particular to voltage scaling DACs, and is more particularly directed toward a fully symmetrical voltage scaling DAC with enhanced output range.
BACKGROUND OF THE INVENTION
Single string voltage scaling DACs produce an analog output voltage by selectively tapping a voltage-divider resistor string connected between high and low reference voltages, with the low reference generally being set at ground.
FIG. 1
illustrates an N-bit converter, generally depicted by the numeral 100, in which a resistor string consisting of resistors R
1
, R
2
, . . . , R
2
N
is connected between a high reference voltage (VREF+) node
2
and a low reference voltage (VREF−) node
4
, which are typically five volts and ground, respectively. The voltage drop across each resistor is equal to one least significant bit (LSB) of output voltage range.
The output is sampled by a decoding switch network, illustrated as switches S
1
, S
2
, . . . , S
2
N
. Each switch taps a different point in the resistor string, so that closing a particular switch while leaving the others open places a unique analog voltage on a common output line
6
to which each of the switches is connected. For an N-bit system, this simple configuration requires 2
N
resistors, 2
N
switches, and 2
N
logic control signals for unipolar switch implementations (one for each switch). For transmission gate switch implementations, 2
N+1
logic control signals are required. Standard, unary binary coding is assumed for purposes of explanation.
One technique of the prior art that attempts to limit the total number of resistors required is described in U.S. Pat. No. 3,997,892 to Susset, and is illustrated in FIG.
2
. The system incorporates a non-linear resistive divider
10
for the MSBs and a linear resistive divider
16
for the LSBs. These resistor strings
10
,
16
are cascaded, with buffers
18
,
20
isolating the current paths between strings. In this implementation, the second LSB impedance string
16
effectively “zooms in” on an individual MSB DAC resistor (R
1
through R
4
). The LSB impedance string
16
serves to sub-divide the voltage range across the MSB resistor, thereby increasing the resolution of the converter. A significant disadvantage of this architecture is that it requires buffers
18
,
20
that dissipate additional power and occupy extra die area while introducing a new and different non-linear error source.
Perhaps one of the most common implementations of the basic voltage-mode DAC of the prior art includes an R/2R ladder network of resistors
20
, as illustrated in
FIG. 3. A
network of switches
22
, generally implemented as MOS transistors, determines the interconnection of the resistive elements either to the positive reference voltage V
REF
or to the negative reference voltage A
GND
. In this embodiment, binary switch impedance scaling is used, as shown in FIG.
3
. The specific switch settings are determined by the individual input code bits. A disadvantage of this architecture is that the total DAC current displays a very strong, non-linear code dependency. The number of resistors required for a DAC implementation can be reduced considerably, in comparison with the simple string DAC, by adopting the DAC of FIG.
4
. In the implementation of
FIG. 4
, the DAC has an input digital code word of N bits, where M of the bits represent the LSBs and N-M of the bits consequently represent the MSBs. This convention, where M of the bits are assumed to represent the LSBs, will be adopted in the subsequent discussions. In
FIG. 4
, the outer resistor strings
10
and
12
decrement the input signal's MSBs, while the inner string
14
decrements the LSBs. Using this technique, the two identical outer strings
10
,
12
of resistors and the inner string
14
have an output range of 0 to 2
N−
1*LSBS. As shown in
FIG. 4
, each of the two outer strings
10
,
12
requires only 2
N−M
−1 resistors, while the inner string
14
needs 2
M
resistors, a considerable savings in component count over the simple string implementation of FIG.
1
.
In selecting a particular combination of switch closures in the embodiment illustrated in
FIG. 4
, the same number of outer string resistors (and they are of equal value) is always interposed between the V
REF+
2
and V
REF−
4
terminals. In other words, the inner string resistors
14
seem to “slide” along the outer strings
10
,
12
.
Yet another variation in voltage scaling DACs of the prior art, as shown in
FIG. 5
, has (2
M
−1) resistors Rb
1
-Rb
3
in the LSB impedance string
33
. In this implementation, the second impedance string
33
is coupled across, or in parallel with, a first impedance string
32
with 2
N−M
resistors, Ra
1
-Ra
4
. The loading effect of the second impedance string
33
in parallel with a resistor of the first impedance string
32
is critical to the architecture. The second impedance string
33
uses a small portion of the current that flows in the first impedance string
32
. The relative portion of the current flowing in the LSB impedance string
33
is dependent on the resolution of the converter and the actual design implementation detail, e.g., MSB DAC vs. LSB DAC resistor scaling and switch impedances. A disadvantage of this DAC architecture is that it manifests a highly non-linear output pin to reference pin impedance versus code transfer function, which renders it unsuitable for potentiometer applications.
A disadvantage of most prior art voltage scaling DAC architectures (with the exception of the DAC described above with reference to
FIG. 5
) is that the architectures are asymmetrical. There are applications in which it would be desirable simply to reverse the analog reference voltages and/or complement the digital inputs without compromising range or linearity. Most prior art architectures are simply incompatible with this type of modification.
A second disadvantage is that the output voltage range of these voltage scaling DAC implementations of the prior art does not extend all the way from the positive reference potential to the negative reference potential. Consequently, a need arises for an economically manufacturable, full-range, symmetrical DAC architecture.
SUMMARY OF THE INVENTION
These needs and others are addressed by the improved voltage scaling DAC of the present invention, in which the LSB resistor string implementation achieves full output range from a voltage scaling DAC with a linear output pin to reference pin impedance versus code transfer function.
In accordance with one aspect of the present invention, an improved N-bit voltage scaling DAC responsive to an N-bit input code word having M LSBs includes first and second outer impedance string segments, each comprising 2
N−M
−1 series-connected impedances of substantially equal value, an inner string of series-connected impedances of substantially equal value having first and second end points, first and second outer string switch networks providing electrical connections between selected outer string impedance terminals and first and second common nodes, and an inner string switch network providing electrical connection between selected inner string impedance terminals and an output node. The inner string of series-connected impedances comprises no more than 2
M
−1 impedances of substantially equal value. The series-connected impedances may comprise controlled MOS devices or resistors.
In one form of the invention, a first end of the first outer impedance string is coupled to a first reference voltage and a second end of the second outer impedance string is coupled to a second reference voltage. The first common node comprises the first inner string end point and the second common node comprises the second inner string end point. In another aspect of the invention, the first common node comprises a first reference voltage and the second common node comprises a second reference voltage.
In another f

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