Arithmetic decode without renormalization costs

Coded data generation or conversion – Digital code to digital code converters – To or from code based on probability

Reexamination Certificate

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C382S238000

Reexamination Certificate

active

11483056

ABSTRACT:
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.

REFERENCES:
patent: 6025932 (2000-02-01), Imanaka
patent: 7183951 (2007-02-01), Bossen

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