Coded data generation or conversion – Digital code to digital code converters – To or from constant distance codes
Reexamination Certificate
2001-09-04
2003-09-09
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from constant distance codes
C341S159000, C341S160000, C341S064000
Reexamination Certificate
active
06617986
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to digital to analogue converters (DAC), and more specifically, to the design of a Gray Code to Thermometer Code decoder circuit for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations.
2. Related Art
High performance SRAMs produced in conformity with the DDR3 specification are required to incorporate on-chip programmable termination at all input pads. The value of digitally adjustable termination resistors are typically programmed to match a multiple of the line impedance, Z
0
, to improve signal integrity in the interface between two chips. Digitally adjustable resistors are digital-to-analog converters (DACs).
Programable Termination Circuitry
A programmable terminator circuit can be constructed from binary weighted devices presenting a tunable impedance at each chip pad. For instance, a 4 bit binary weighted termination circuit has 4 devices of widths 1×, 2×, 4×, 8×, for a total width of 15×. The gate inputs to theses devices are driven by the latched outputs of a 4 bit binary code counter. This design has the disadvantage of possibly changing multiple bits as the count is incremented or decremented by one. For example, if the 4-bit count is incremented from 7 to 8, the binary count changes from 0111 to 1000; all four bits change. If timing skews or noise is present, it is possible to see a count of 0000 (max. impedance), or 1111 (min. impedance), or various other combinations while the bits are changing from 7 to 8. If the skew
oise is moderate, these transient counts appear as impedance glitches on the interface which can reduce signal integrity. If the skew
oise is more severe, it is possible to get an ‘impartial count update’ if the incorrect state of any bit is latched into downstream registers.
Using Gray code counting (in conjunction with Unary/Thermometer code decoding—discussed below) avoids the problem discussed above of simultaneously changing multiple bits since only one bit changes as the count is incremented or decremented by one. For instance, changing the count from 7 to 8, results in the equivalent Gray code count changing from 0100 to 1100; only one bit (the MSB) changes. Even if severe skew
oise is present, the contents of downstream latches will either remain 0100 or get updated to 1100.
Equally weighted termination devices can be used in place of binary weighted device sizes. An equally weighted termination circuit has 15 devices of 1× width and a total width of 15×. The equally weighted termination circuit however requires that the 4 bit Gray code count be decoded into a 15-bit unary code count (e.g., a redundant Thermometer code wherein, e.g., 10010101101101 equals 001110101101010). A thermometer-coded scheme can be improved by using resistive device-shape factors that produce incremental changes in conductance that are a fixed percentage of accumulated conductance. This idea leads to a slowly tapering set of sizes in the resistor elements. See generally, Digital Systems Engineering, Dally (Cambridge U. Press 1999) section 11.1.3.2.
Table 1 is a logic table illustrating how a 4-Bit Gray code to 15-Bit Thermometer code Decoder would operate in logical theory, wherein all Thermometer code outputs 1-15 are active-high (i.e., a High voltage indicated symbolically by a “1” characterizes the “active” state of the active-high output).
TABLE 1
4-Bit Gray code to 15-Bit Thermometer Code Example
Thermometer
Gray
Code
Decimal
Code
111111000000000
Count
DCBA
543210987654321
0
0000
000000000000000
1
0001
000000000000001
2
0011
000000000000011
3
0010
000000000000111
4
0110
000000000001111
5
0111
000000000011111
6
0101
000000000111111
7
0100
000000001111111
8
1100
000000011111111
9
1101
000000111111111
10
1111
000001111111111
11
1110
000011111111111
12
1010
000111111111111
13
1011
001111111111111
14
1001
011111111111111
15
1000
111111111111111
FIG. 2
illustrates the manner in which a real 4-Bit Gray code to 15-Bit Thermometer code Decoder would operate in real time while monotonically incrementing from Thermometer code count 0 to count 15. The Gray code count is sequentially incremented from count zero to count 15 via bits A, B, C, & D which results in the Thermometer code count incrementing from count zero to count 15 via bits 1-15.
An advantage of the Gray code to Thermometer code system is that the magnitude of any potential impedance glitch is further reduced, since when the impedance count is updated (e.g., incremented or decremented by a single unit), a single device of width=1× is either enabled (counting up) or disabled (counting down). This corresponds to a relatively small change in the total value of the termination impedance and produces a smaller glitch on the interface than that produced when multiple devices are switched (as may occur in a binary weighted system). Also, the potential for a relatively large change in terminator impedance due to an “impartial count update” is eliminated.
FIG. 3
depicts a topology of a simple Combinational Logic Decoder
100
that utilizes Combinational logic circuits to convert Gray code into Thermometer code (FIG.
3
). This topology includes one cell per output bit, each cell being adapted to be activated by a particular count of the gray code or any higher count. For example, 15 cells would correspond to the 15 output bits of Thermometer code, and upon the occurrence of count 15, all 15 cells would be active. Each cell contains different Combinational logic circuitry (e.g., a different selection or arrangement of Combinational logic gates) corresponding to the specific input/output relationship of each cell. The output of each cell depends solely on the Gray coded inputs and is independent of the outputs of other cells. To output the desired Thermometer code, the corresponding Gray code is inputted without any reset. To set the Thermometer code to a different value, the new Gray code is inputted without any reset command. The Combinational cells have no memory or feedback mechanisms. The past output values have no bearing on current output values. Thus, if the Gray code input value changes by more than one (e.g., from a Gray coded 1 to a Gray coded 4,) the Thermometer code output will change by more than one (e.g., by 3).
FIGS. 4
,
5
and
6
each show the combinational (i.e., combinatorial) logic within one the cells depicted in FIG.
3
. The output of these cells directly corresponds to the above Thermometer code in Table 1.
FIG. 4
depicts exemplary combinational logic gates within CELL1 of the simple Combinational Logic Decoder
100
of FIG.
3
. CELL1 can be implemented with a NAND gate (1NAND) composed of 8 CMOS (Complementary Metal Oxide Semiconductor) transistors (i.e, the device count in CELL1 is 8).
FIG. 5
depicts exemplary combinational logic gates within CELL3 of the simple Combinational Logic Decoder
100
of FIG.
3
. CELL3 can be implemented with two (cascaded) NAND gates (3NAND1 and 3NAND2) composed of 10 CMOS transistors (i.e, the device count in CELL3 is 10).
FIG. 6
depicts exemplary combinational logic gates within CELL13 of the simple Combinational Logic Decoder
100
of FIG.
3
. CELL13 can be implemented with three (cascaded) gates (13NAND1, 13NOR1, 13NOR2) composed of 12 CMOS transistors.
BRIEF SUMMARY OF THE INVENTION
The disclosed Area Efficient Sequential Decoder (AESD) topology (illustrated by the exemplary 4-Gray-code-bit decoder
200
in
FIG. 8
a
) overcomes the limitations of a combinational logic decoder (e.g., decoder
100
of
FIG. 3
) for decoding a gray coded count into a unary coded count (e.g., thermometer coded count). The disclosed AESD topology (see
FIG. 8
a
) provides a lower device count when compared to the simple combinational logic solution
100
. For example, for a 4 Gray code bit to 15 Thermometer code bit decoder, the AESD topology (
200
) uses only 90 (or fewer, see optimization methods discussed below) devices. The simple Combinational logic solution (See
F
Connor John
Hansen Patrick R.
Leschuk Steven
Rotella Jason E.
Henkler Richard A.
Nguyen John
Young Brian
LandOfFree
Area efficient, sequential gray code to thermometer code... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Area efficient, sequential gray code to thermometer code..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Area efficient, sequential gray code to thermometer code... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3050967