Architecture for multi-stage decoding of a CABAC bitstream

Coded data generation or conversion – Digital code to digital code converters – To or from code based on probability

Reexamination Certificate

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C341S051000, C341S106000

Reexamination Certificate

active

07839311

ABSTRACT:
Techniques for optimizing the Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream decoding are disclosed. In one configuration, a device has a first processing circuit operative to decode a Context-based Adaptive Binary Arithmetic Coding (CABAC) bitstream into an intermediate signal having a CABAC decoded standard format and a decoded order. A second processing circuit decodes the intermediate signal using a non-CABAC decoding standard. A buffer is provided between the first and second processing circuits to improve processing speeds.

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patent: 6917310 (2005-07-01), Pearson et al.
patent: 6927710 (2005-08-01), Linzer et al.
patent: 7301485 (2007-11-01), Senda
patent: 2004/0085233 (2004-05-01), Linzer et al.
patent: 2004/0260739 (2004-12-01), Schumann
patent: 2004/0263361 (2004-12-01), Pearson et al.
patent: 2006/0126744 (2006-06-01), Peng et al.
patent: 1684435 (2006-07-01), None
patent: WO 2006051796 (2006-05-01), None
ITU-T H.264, “Advanced Video Coding for Generic Audio Visual Services”, Mar. 2005, sections 7.3.4, 7.3.5, and 9.3.

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