I/O Bus transceiver for a data processing system

Details I/O Bus transceiver for a data processing system I/O Bus transceiver for a data processing system

1976-02-27

1977-09-06

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 304

Patent

active

040472019

ABSTRACT:
There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or apparatus for interfacing with an I/O bus (bus structure). The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.

REFERENCES:
patent: 3341820 (1967-09-01), Grillmeier et al.
patent: 3388349 (1968-06-01), Ault
patent: 3528060 (1970-08-01), Streif
patent: 3541513 (1970-11-01), Paterson
patent: 3564509 (1971-02-01), Perkins et al.
patent: 3566031 (1971-02-01), Carbone et al.
patent: 3771135 (1973-11-01), Huettner et al.

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