I/O Bus clock

Details I/O Bus clock I/O Bus clock

1982-09-28

1985-05-21

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 104

Patent

active

045190348

ABSTRACT:
Fully synchronous operation is provided by the use of separate frame and clock signals in each of the two directions relative to the IOCP, with all these signals controlled by the IOCP. The transmit (outbound) clock and frame signals (TCLK and TFRM) are simply sent on two lines from the IOCP to a bus terminator at the far end with the devices connecting to these lines in sequence. The receive (inbound) clock and frame signals (RCLK and RFRM) also originate at the IOCP, but their lines go directly to the far end where they are turned around and sent back to the IOCP with the devices being coupled to these lines in the reverse sequence. This provides a pair of signals that travel toward the IOCP but are still controlled by it for timing the incoming data.

REFERENCES:
patent: 4047201 (1977-09-01), Kerllenevich
patent: 4053950 (1977-10-01), Bourke et al.
patent: 4056843 (1977-11-01), Bishop et al.
patent: 4079448 (1978-03-01), N'Guyen et al.
patent: 4335426 (1982-06-01), Maxwell et al.
patent: 4365297 (1982-12-01), Grisham, Jr.

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