I/O Controller for transferring data between a host processor an

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G06F 1300

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active

043719325

ABSTRACT:
An I/O controller for transferring data between a host processor and one or more I/O devices. This I/O controller includes a microprocessor, a direct memory access controller and a dual port storage unit, one port of which is coupled to the host processor I/O channel bus and the other port of which is coupled to the microprocessor bus. All data transfers are by way of the dual port storage unit. The I/O controller includes an interleaving mechanism for enabling concurrent performance of two different modes of data transfer between the host processor and the I/O controller. In particular, this interleaving mechanism enables host processor direct program control (DPC) data transfers to be performed at the same time that the I/O controller is busy doing cycle steal data transfers for a block of data. These DPC data transfers are accomplished without interrupting the cycle stealing operations.

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patent: 4137565 (1979-01-01), Mager
patent: 4156932 (1979-05-01), Robinson
Rothlisberger, a paper entitled "A Standard Bus for Multiprocessor Architecture", appearing in a book entitled Microcomputer Architecture, North-Holland Publishing Company, 1977.
Adams et al: "Design Motivations for Multiple Processor Microcomputer Systems", Computer Design, 3/78.
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Kinnie: "Dual-Port RAM Hikes Throughput in I/O Controller Board", Electronics, pp. 107-112, 8/17/78.
Samuelson: "Intelligent Controller Increases Data Throughput, Reduces Host OVerhead", Computer Design, 120-126, 7/79.
Motorola Semiconductor Products Inc.: MC6881/MC3449 Triple Bi-Directional Bus Switch.

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