I/O bus transceiver for a data processing system

Details I/O bus transceiver for a data processing system I/O bus transceiver for a data processing system

1977-01-10

1977-09-06

Springborn, Harvey E.

Boots, shoes, and leggings

178 59, G06F 304, H04L 514

Patent

active

040472469

ABSTRACT:
There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure of interfacing structure for interfacing with I/O structure. The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.

REFERENCES:
patent: 3388349 (1968-06-01), Aurt
patent: 3566031 (1971-02-01), Chrbone et al.
patent: 3730993 (1973-05-01), Moriyasu
patent: 3771135 (1973-11-01), Huettner et al.
patent: 3899637 (1975-08-01), Willard et al.
patent: 3931615 (1976-01-01), Oliver et al.
patent: 3932841 (1976-01-01), Deerfield et al.
patent: 3934232 (1976-02-01), Curley et al.

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