I/O Adapter with direct memory access to I/O control information

Details I/O Adapter with direct memory access to I/O control information I/O Adapter with direct memory access to I/O control information

1981-11-19

1984-10-02

Smith, Jerry

Boots, shoes, and leggings

G06F 300

Patent

active

044751559

ABSTRACT:
A data proessing system includes a processor, a memory, a direct memory accessing (DMA) control unit and an input/output adapter. A memory area of a given capacity is reserved in the memory for storing control information transferred between the processor and the adapter. For transfer of the control information, the adapter accesses the control information stored in the memory area through direct memory accessing under control of the DMA control unit while the processor can make access to the control information through a memory read/write command. By storing at the predetermined area of the memory the control information transferred between the processor and the adapter, the quantity of hardware and the number of IC's required for implementing the adapter can be significantly reduced. Conflicting access requests to the main memory area by the processor and adapter are prevented through time-division control of the memory bus.

REFERENCES:
patent: 4133030 (1979-01-01), Huettner et al.
patent: 4325119 (1982-04-01), Grandmaison et al.
patent: 4328543 (1982-05-01), Brickman et al.
patent: 4346437 (1982-08-01), Blahut et al.
patent: 4346439 (1982-08-01), Huno et al.
PDP11/45 Processor Handbook, p. 233, Digital Equipment Corporation, 1971.
PDP11 Peripherals and Interfacing Handbook, pp. 281, 286, 287, Digital Equipment Corporation, 1971.

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