I/O bus to system interface

Details I/O bus to system interface I/O bus to system interface

1992-07-07

1993-11-09

Fleming, Michael R.

Boots, shoes, and leggings

395250, 364DIG1, 3642285, 3642383, 3642385, 3642386, 364239, 3642391, 3642395, 3642356, 3642397, 364240, 3642403, 3642405, 3642456, 3642457, 3642513, 364260, 364270, 3642702, 3642706, G06F 300, G06F 1300

Patent

active

052610578

ABSTRACT:
An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurality of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.

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