Semiconductor device with speed binning test circuit and...

Details Semiconductor device with speed binning test circuit and... Semiconductor device with speed binning test circuit and...

2007-08-21

2007-08-21

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C257S048000, C331S057000, C326S016000

Reexamination Certificate

active

10720123

ABSTRACT:
A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning test circuit may also include a plurality of pads. Each pad may be arranged between a pair of circuit groups so that at least one output terminal of a unit delay circuit of one of the plurality of circuit groups is connected to one of the pads. The speed binning test device performs a speed binning test method in which a signal through the circuit groups is delayed, and on-chip-variations are monitored to determine a total signal delay time through the chain structure.

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Korean Office Action, Notice to Submit Response, Jan. 20, 2005 (English translation provided).

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