4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Hoi-Jin Lee

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Apparatus, generator, and method for clock tree synthesis

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Branch predictor suitable for multi-processing microprocessor

Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate

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Cache system having branch target address cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Cache system having branch target address cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Method of HDL simulation considering hard macro core with...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2334913

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