Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-17
2003-05-20
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S655000, C438S682000, C438S683000
Reexamination Certificate
active
06566214
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The invention relates generally to semiconductor device manufacturing and, more particularly, to using a silicide hard mask to pattern a gate electrode.
B. Description of the Related Art
In a conventional metal oxide semiconductor field effect transistor (MOSFET), the gate electrode includes a lower layer of doped polysilicon and an upper layer of metal silicide, such as titanium silicide. The metal silicide layer is conventionally formed by the salicide process illustrated in
FIGS. 1A-E
. Field oxide regions
2
and gate oxide layer
3
are formed on a silicon substrate
1
. A polysilicon layer
5
is then formed on the gate oxide layer
3
, as illustrated in FIG.
1
A. The polysilicon layer
5
and the gate oxide layer
3
are then patterned by conventional photolithography to form a lower gate electrode layer
5
A and a gate oxide
3
A. Lightly doped source and drain regions
7
A,
9
A are then implanted into the substrate
1
, using the gate electrode layer
5
A as a mask, as shown in
FIG. 1B. A
silicon oxide layer is then deposited over the lower gate electrode layer
5
A and anisotropically etched to form sidewall spacers
11
A and
11
B. Heavily doped source and drain regions
7
B,
9
B are then implanted into the substrate
1
using the lower gate electrode layer
5
A and the sidewall spacers
11
A,
11
B as a mask, as shown in
FIG. 1C. A
metal layer
13
, such as a titanium layer, is then deposited on the polysilicon gate electrode layer
5
A, the sidewall spacers
11
A,
11
B and the exposed doped silicon source
7
B and drain regions
9
B, as illustrated in FIG.
1
D. The resulting device is then annealed to react the metal layer
13
with the exposed polysilicon lower gate electrode layer
5
A to form an upper metal silicide gate electrode layer
15
on the lower polysilicon gate electrode layer
5
A and metal silicide contact layers
17
,
19
on the source
7
B and drain regions
9
B. The metal layer
13
does not substantially react with the oxide sidewall spacers
11
A,
11
B. The portions of the metal layer
13
remaining over the spacers
11
A,
11
B are removed by a selective etch, which does not remove the silicide layers
15
,
17
and
19
, as shown in FIG.
1
E.
The above described salicide process works well for wide gate electrodes. However, the present inventors have determined that when the salicide process is used to form narrow gate electrodes, for example gate electrodes having a width of less than 0.25 microns, such gate electrodes suffer from poor conductivity and poor contact resistance. Thus, it is desirable to improve the conductivity and contact resistance of a narrow gate electrode containing a lower polysilicon layer and an upper metal silicide layer.
SUMMARY OF THE INVENTION
According to one preferred aspect of the present invention, there is provided a method of making a semiconductor device, comprising forming a polysilicon layer over a substrate, forming a metal layer on the polysilicon layer, annealing the metal layer and the polysilicon layer to form a metal silicide layer on the polysilicon layer, patterning the metal silicide layer, and patterning the polysilicon layer using the patterned metal silicide layer as a mask.
According to another preferred aspect of the present invention, there is provided a method of making a semiconductor device, comprising forming a polysilicon layer over a substrate, forming a metal layer on the polysilicon layer, annealing the metal layer and the polysilicon layer to form a metal silicide layer on the polysilicon layer, forming a photoresist layer on the metal silicide layer, exposing the photoresist layer to radiation, patterning the photoresist layer to form a photoresist etching mask having a first width, etching the metal silicide layer using the photoresist etching mask as a mask to form a patterned metal silicide layer having a second width less than the first width, and etching the polysilicon layer using the patterned metal silicide layer as a mask.
According to another preferred aspect of the present invention, there is provided a method of making a MOSFET, comprising forming a gate insulating layer on a substrate, forming a polysilicon layer on the gate insulating layer, forming a metal layer on the polysilicon layer prior to patterning the polysilicon layer, annealing the metal layer and the polysilicon layer to form a metal silicide layer on the polysilicon layer, forming a photoresist layer on the metal silicide layer, exposing the photoresist layer to radiation, patterning the photoresist layer to form a photoresist etching mask having a first width, patterning the metal silicide layer using the photoresist etching mask as a mask to form an upper layer of a gate electrode, patterning the polysilicon layer using the patterned metal silicide layer as a mask to form a lower gate electrode layer, doping the substrate to form first doped source and drain regions having a first doping concentration using the gate electrode as a mask, and forming conductive contacts on the first doped source and drain regions.
REFERENCES:
patent: 4460435 (1984-07-01), Maa
patent: 4818715 (1989-04-01), Chao
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5160407 (1992-11-01), Latchford et al.
patent: 5283449 (1994-02-01), Ooka
patent: 5431770 (1995-07-01), Lee et al.
patent: 5498555 (1996-03-01), Lin
patent: 5605854 (1997-02-01), Yoo
patent: 5955761 (1999-09-01), Yoshitomi et al.
patent: 6046098 (2000-04-01), Iyer
patent: 6069044 (2000-05-01), Wu
patent: 6127249 (2000-10-01), Hu
patent: 6159856 (2000-12-01), Nagano
patent: 6204105 (2001-03-01), Jung
Stanley Rolf: “Silicon Processing for the VLSI Era, vol. 2: Process Integration,” 1990, pp. 144-152, Lattice Press, Sunset Beach, California.
Bell Scott A.
Lukanc Todd P.
Lyons Christopher F.
Plat Marina V.
Subramanian Ramkumar
Foley & Lardner
Jr. Carl Whitehead
Smoot Stephen W.
LandOfFree
Method of making a semiconductor device by annealing a metal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a semiconductor device by annealing a metal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a semiconductor device by annealing a metal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3090563