4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Boryau (Jack) Sheu

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Mask network design for scan-based integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Mask network design for scan-based integrated circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Method and apparatus for broadcasting test patterns in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and apparatus for multi-level scan compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method for performing ATPG and fault simulation in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2946929

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