Oxide etch process using hexafluorobutadiene and related...

Details Oxide etch process using hexafluorobutadiene and related... Oxide etch process using hexafluorobutadiene and related...

1998-11-16

2001-01-16

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

C216S068000, C216S072000, C438S723000, C438S738000, C438S743000

Reexamination Certificate

active

06174451

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to etching of silicon integrated circuits. In particular, the invention relates to etching silicon oxide and related materials in a process that is capable of greatly reduced etching rates for silicon nitride and other non-oxide materials but still producing a vertical profile in the oxide.
BACKGROUND ART
In the fabrication of silicon integrated circuits, the continuing increase in the number of devices on a chip and the accompanying decrease in the minimum feature sizes have placed increasingly difficult demands upon many of the many fabrication steps used in their fabrication including depositing layers of different materials onto sometimes difficult topologies and etching further features within those layers.
Oxide etching has presented some of the most difficult challenges. Oxide is a somewhat generic term used for silica, particularly silicon dioxide (SiO
2
) although slightly non-stoichiometric compositions SiO
x
are also included, as is well known. The term oxide also covers closely related materials, such as oxide glasses including borophosphosilicate glass (BPSG). Some forms of silicon oxynitride are considered to more closely resemble a nitride than an oxide. Small fractions of dopants such as fluorine or carbon may be added to the silica to reduce its dielectric constant. Oxide materials are principally used for electrically insulating layers, often between different levels of the integrated circuit. Because of the limits set by dielectric breakdown, the thickness of the oxide layers cannot be reduced to much below 0.5 to 1 &mgr;m. However, the minimum feature sizes of contact and via holes penetrating the oxide layer are being pushed to well below 0.5 &mgr;m. The result is that the holes etched in the oxide must be highly anisotropic and must have high aspect ratios, defined as the depth to the minimum width of a hole. A further problem arises from the fact that the underlying silicon may be formed with active doped regions of thicknesses substantially less than the depth of the etched hole (the oxide thickness). Due to manufacturing variables, it has become impossible to precisely time a non-selective oxide etch to completely etch through the silicon oxide without a substantial probability of also etching through the underlying active silicon region.
The anisotropy can be achieved in dry plasma etching in which an etching gas, usually a fluorocarbon, is electrically excited into a plasma. The plasma conditions may be adjusted to produce highly anisotropic etching in many materials. However, the anisotropy should not be achieved by operating the plasma reactor in a pure sputtering mode in which the plasma ejects particles toward the wafer with sufficiently high energy that they sputter the oxide. Sputtering is generally non-selective, and high-energy sputtering also seriously degrades semiconducting silicon exposed at the bottom of the etched contact hole.
In view of these and other problems, selective etching processes have been developed which depend more upon chemical effects. These processes are often described as reactive ion etching (RIE). A sufficiently high degree of selectivity allows new structures to be fabricated without the need for precise lithography for each level.
An example of such an advanced structure is a self-aligned contact (SAC), illustrated in the cross-sectional view of
FIG. 1. A
SAC structure for two transistors is formed on a silicon substrate
2
. A polysilicon gate layer
4
, a tungsten silicide barrier and glue layer
6
, and a silicon nitride cap layer
8
are deposited and photolithographically formed into two closely spaced gate structures
10
having a gap
12
therebetween. Chemical vapor deposition is then used to deposit onto the wafer a substantially conformal layer
14
of silicon nitride (Si
3
N
4
), which coats the top and sides of the gate structures
10
as well as the bottom
15
of the gap
12
. In practice, the nitride deviates from the indicated stoichiometry and may have a composition of SiN
x
, where x is between 1 and 1.5. The nitride acts as an electrical insulator. Dopant ions are ion implanted using the gate structures
10
as a mask to form a self-aligned p-type or n-type well
16
, which acts as a common source for the two transistors having respective gates
10
. The drain structures of the transistors are not illustrated.
An oxide field layer
18
is deposited over this previously defined structure, and a photoresist layer
20
is deposited over the oxide layer
18
and photographically defined into a mask so that a subsequent oxide etching step etches a contact hole
22
through the oxide layer
18
and stops on the portion
24
of the nitride layer
14
underlying the hole
22
. It is called a contact hole because the metal subsequently deposited into the contact hole
22
contacts silicon rather than a metal layer. A post-etch sputter removes the nitride portion
24
at the bottom
15
of the gap
12
. The silicon nitride acts as an electrical insulator for the metal, usually aluminum, thereafter filled into the contact hole
22
.
Because the nitride acts as an insulator, the SAC structure and process offer the advantage that the contact hole
22
may be wider than the width of the gap
12
between the gate structures
10
. Additionally, the photolithographic registry of the contact hole
22
with the gate structures
10
need not be precise. However, to achieve these beneficial effects, the SAC oxide etch must be highly selective to nitride. That is, the process must produce an oxide etch rate that is much greater than the nitride etch rate. Numerical values of selectivity are calculated as the ratio of the oxide to nitride etch rates. Selectivity is especially critical at the corners
26
of the nitride layer
14
above and next to the gap
12
since the corners
26
are the portion of the nitride exposed the longest to the oxide etch. Furthermore, they have a geometry favorable to fast etching that tends to create facets at the corners
26
.
Furthermore, increased selectivity is being required with the increased usage of chemical mechanical polishing (CMP) for planarization of an oxide layer over a curly wafer. The planarization produces a flat oxide surface over a wavy underlayer substrate, thereby producing an oxide layer of significantly varying thickness. As a result, the time of the oxide etch must be set significantly higher, say by 100%, than the etch of the design thickness to assure penetration of the oxide. This is called over etch, which also accounts for other process variations. However, for the regions with a thinner oxide, the nitride is exposed that much longer to the etching environment.
Ultimately, the required degree of selectivity is reflected in the probability of an electrical short between the gate structures
10
and the metal filled into the contact hole
22
. The etch must also be selective to photoresist, for example at facets
28
that develop at the mask corners, but the requirement of photoresist selectivity is not so stringent since the photoresist layer
20
may be made much thicker than the nitride layer
14
.
In the future, the most demanding etching steps are projected to be performed with high-density plasma (HDP) etch reactors. Such HDP etch reactors achieve a high-density plasma having a minimum average ion density of 10
11
cm
−3
across the plasma exclusive of the plasma sheath. Although several techniques are available for achieving a high-density plasma such as electron cyclotron resonance and remote plasma sources, the commercially most important technique involves inductively coupling RF energy into the source region. The inductive coil may be cylindrically wrapped around the sides of chamber or be a flat coil above the top of the chamber or represent some intermediate geometry.
An example of an inductively coupled plasma etch reactor is the IPS etch reactor, which is also available from Applied Materials and which by Collins et al. describe in U.S. patent application, Ser. No. 08/733,544, filed

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