Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2005-10-12
2008-03-18
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S014000, C438S018000, C438S508000, C324S755090
Reexamination Certificate
active
07345305
ABSTRACT:
A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
REFERENCES:
patent: 7098054 (2006-08-01), Filippi et al.
U.S. Appl. No. 10/726,140, Habib Hichri et al.
Hance H. Huston and C. Patrick Clarke: “Reliability Defect Detection and Screening during Processing—Theory and Implementations”; IEEE/IRPS; Jan. 1992; pp. 268-275.
R. G. Filippi et al.; “Thermal Cycle Reliability of Stacked Via Structures with Copper Metallization and an Organic Low-K Dielectric”; sent in Oct. 2003 to International Reliability Physics Symposium committee for later publishing; 4 pages (including 2004 IRPS Submission Cover Page and article).
R. G. Filippi et al.; “Thermal Cycle Reliability of Stacked Via Structures with Copper Metallization and an Organic Low-K Dielectric”; IBM Hopewell Junction, NY Yorktown Heights, NY, Essex Junction, VT; Feb. 20, 2004; 7 pages.
Filippi Ronald Gene
Gignac Lynne Marie
McGahay Vincent J.
Murray Conal Eugene
Rathore Hazara Singh
Keusey, Tutunjian & & Bitetto, P.C.
Le Dung A.
Trepp, Esq. Robert M.
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