Coating apparatus – Gas or vapor deposition – With treating means
Reexamination Certificate
2001-04-24
2003-02-04
Mills, Gregory (Department: 1763)
Coating apparatus
Gas or vapor deposition
With treating means
C118S715000, C156S345430
Reexamination Certificate
active
06513452
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to plasma chambers used for fabricating semiconductor devices. More specifically, this invention relates to apparatus and methods of adjusting the DC bias voltage on one or more chamber electrodes to which RF power is applied.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor devices, plasma chambers commonly are used to perform various fabrication processes such as etching, chemical vapor deposition (CVD), and sputtering. Generally, a vacuum pump maintains a very low pressure within the chamber while a mixture of process gases continuously flows into the chamber and an electrical power source excites the gases into a plasma state. The constituents of the process gas mixture are chosen to effect the desired fabrication process.
In essentially all etching and CVD processes, and in many sputtering processes, the semiconductor wafer or other workpiece is mounted on a cathode electrode, and a radio frequency (RF) electrical power supply is connected, through a DC blocking capacitor, between the cathode electrode and an anode electrode in the chamber. Most commonly, the walls of the chamber are metal and are connected to the RF power supply to function as the anode electrode. When the chamber walls are the anode, they typically are connected to electrical ground.
The body of the plasma has a positive charge such that its average DC voltage is positive relative to the cathode and anode electrodes. Because the RF power supply is connected to the cathode and anode electrodes through a DC blocking capacitor, the respective DC voltages at the cathode and anode can be unequal. Specifically, because the cathode's surface area facing the plasma is much smaller than the anode's surface area facing the plasma, the cathode is much more negative than the anode. In other words, the voltage drop between the plasma body and the cathode is much greater than the voltage drop between the plasma body and anode. This voltage asymmetry is a widely observed phenomenon, although its physical cause is complex and not completely understood. (See M. A. Lieberman et al., “Principles of Plasma Discharges and Materials Processing,” pub. John Wiley & Sons, 1994, pages 368-372.) The negative DC voltage at the cathode relative to the anode commonly is referred to as the “cathode DC bias”.
The negative DC bias voltage at the cathode accelerates ions from the plasma to bombard the semiconductor wafer with a kinetic energy approximately equal to the voltage drop between the cathode and the plasma body. The kinetic energy of the bombarding ions can be beneficial in promoting the chemical or physical reactions desired for the semiconductor fabrication process.
However, bombarding ions having excessive kinetic energy can damage the device structures being fabricated on the semiconductor wafer. Therefore, it often is desirable to reduce the cathode DC bias.
A known method of reducing the cathode DC bias is to reduce the level of RF power applied to the cathode electrode. However, reducing the RF power undesirably reduces the rate of dissociation of molecules in the plasma, thereby undesirably reducing the rate at which the fabrication process is carried out (i.e., increasing the time required to fabricate a semiconductor device). Therefore, a need exists for an apparatus and method for reducing the cathode DC bias other than by reducing the RF power supplied to the cathode.
Certain semiconductor fabrication processes require more highly energetic ion bombardment than other processes. It is desirable for a single plasma chamber to be adaptable to a number of different processes. Therefore, a need exists for a method of adjusting the cathode DC bias in a given chamber other than by adjusting the RF power supplied to the cathode.
SUMMARY OF THE INVENTION
In one aspect, the present invention is a method of adjusting the DC bias on one chamber electrode relative to another electrode by interposing a dielectric shield between one of the electrodes and the plasma. Adjusting any property of the shield which alters the capacitance between the plasma and the electrode covered by the shield can be used to adjust the DC bias. Specifically, the DC bias is adjusted by any of the following adjustments: (1) changing the thickness of the dielectric in the shield; (2) substituting a dielectric material having a different dielectric constant; (3) changing the size or shape of the dielectric to change the surface area of the electrode which is covered thereby; or (4) changing the gap between the shield and the covered electrode.
In particular, the method is useful to adjust or reduce the DC bias voltage at the cathode electrode in a plasma chamber in which the anode electrode includes an electrically grounded chamber wall. The dielectric shield is positioned between the plasma and a selected portion of the electrically grounded components of the chamber, such as the chamber wall. The method permits reducing the magnitude of the negative DC bias voltage at the cathode (relative to the anode) without reducing the RF power applied to the cathode.
In another aspect, the present invention is a plasma chamber for fabricating semiconductor devices having an exhaust baffle which reduces the cathode DC bias by reducing the effective surface area of the electrically grounded chamber wall which couples RF power to the plasma. Specifically, the exhaust baffle has a number of sinuous passages, and the baffle overlies the exhaust port of the plasma chamber so that chamber gases exhausted from the chamber by the vacuum pump pass through the sinuous passages. Each passage is sufficiently long and sinuous that no portion of the plasma within the chamber can extend beyond the outlet of the passage.
The exhaust baffle of the invention electrically isolates the plasma from the portion of the chamber wall behind the baffle, thereby reducing the effective surface area of the grounded chamber wall which couples RF power to the plasma. This reduces the ratio of the effective chamber wall surface area facing the plasma to the cathode surface area facing the plasma, thereby advantageously reducing the magnitude of the negative DC bias at the cathode.
To further reduce the cathode DC bias, the exhaust baffle can include dielectric material. Preferably, the dielectric isolates any electrically conductive elements in the exhaust baffle from the grounded chamber wall. The dielectric should be substantially thicker than the width of the plasma sheath or, alternatively, of sufficient thickness to substantially impede the coupling of RF power from the chamber wall to the plasma via the exhaust baffle.
REFERENCES:
patent: 3904505 (1975-09-01), Aisenberg
patent: 4131533 (1978-12-01), Bialko et al.
patent: 4367114 (1983-01-01), Steinberg et al.
patent: 4491496 (1985-01-01), Laporte et al.
patent: 4496448 (1985-01-01), Tai et al.
patent: 4512283 (1985-04-01), Bonifield et al.
patent: 4590042 (1986-05-01), Drage
patent: 4609347 (1986-09-01), Yamashita et al.
patent: 4802968 (1989-02-01), Hendrix et al.
patent: 4817558 (1989-04-01), Itoh
patent: 5044311 (1991-09-01), Mase et al.
patent: 5047115 (1991-09-01), Charlet et al.
patent: 5065698 (1991-11-01), Koike
patent: 5069938 (1991-12-01), Lorimer et al.
patent: 5125360 (1992-06-01), Nakayama et al.
patent: 5137610 (1992-08-01), Shumate et al.
patent: 5210055 (1993-05-01), Nakaguma et al.
patent: 5210466 (1993-05-01), Collins et al.
patent: 5271963 (1993-12-01), Eichman et al.
patent: 5273588 (1993-12-01), Foster et al.
patent: 5304279 (1994-04-01), Coultas et al.
patent: 5332468 (1994-07-01), Engelhardt
patent: 5336355 (1994-08-01), Zarowin et al.
patent: 5366585 (1994-11-01), Robertson et al.
patent: 5399387 (1995-03-01), Law et al.
patent: 5413673 (1995-05-01), Fujimoto
patent: 5415728 (1995-05-01), Hasegawa et al.
patent: 5441568 (1995-08-01), Cho et al.
patent: 5534751 (1996-07-01), Lenz et al.
patent: 5556501 (1996-09-01), Collins et al.
patent: 5558717 (1996-09-01), Zhao et al.
patent: 5573596 (1996-11-01), Yin
patent: 5605637 (1997-02-01),
Blume Richard
Carducci James D.
Lee Evans Y.
Luscher Paul E.
Pu Bryan Y.
Applied Materials Inc.
Bach Joseph
Hassanzadeh P.
Mills Gregory
Stern Robert J.
LandOfFree
Adjusting DC bias voltage in plasma chamber does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adjusting DC bias voltage in plasma chamber, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adjusting DC bias voltage in plasma chamber will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3183183