All-MOS precision differential delay line with delay a programma

Arrangement of data cells and neural network system utilizing su

Charge coupled device memory with enhanced access features

Compact expandable folded first-in-first-out queue

Control memory using recirculating shift registers for a TDM swi

Digital system having high speed buffering

Fast access charge coupled device memory organizations for a sem

Fast access charge coupled device memory organizations for a sem

Fast access charge coupled device memory organizations for a sem

Micro magnetic core memory

Multiplexed MOS multiaccess memory system

Programmable dynamic shift register with variable shift control

Random access memory with volatile data storage

Recirculating delay line time compressor having plural input tap

Recirculating loop memory array having a shift register buffer f

Recirculating memory with plural input-output taps

Rotating register utilizing field effect transistors

Semiconductor device with prompt timing stabilization

Sequential-access memory

Serial access memory with reduced loop-line delay