Serial access memory with reduced loop-line delay

Details Serial access memory with reduced loop-line delay Serial access memory with reduced loop-line delay

1997-07-28

1998-09-01

Fears, Terrell W.

Static information storage and retrieval

Recirculation stores

365 78, 365233, G11C 1300

Patent

active

058019812

ABSTRACT:
According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an enabling signal that enables access to a certain number of bits at a time. By operating together, the shift registers enable simultaneous access to a multiple of that number of bits. This multiple can be varied to design serial access memories with different word widths. According to another aspect of the invention, there need be only one shift register, but its stages are interleaved. The enabling signal is shifted from a first end of the shift register to a second end, skipping every other stage, then shifted back from the second end to the first end through the stages that were skipped. This operation is repeated cyclically.

REFERENCES:
patent: 4566040 (1986-01-01), Ozawa et al.
patent: 5117388 (1992-05-01), Nakano et al.
Dense static RAM speed data access in memory-intensive systems William Righter 2328 Electronic Design Oct. 4, 1984, No. 20, Waseca, Minnesota, pp. 245-252.

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