All-MOS precision differential delay line with delay a programma

Details All-MOS precision differential delay line with delay a programma All-MOS precision differential delay line with delay a programma

1995-11-17

1997-01-28

Fears, Terrell W.

Static information storage and retrieval

Recirculation stores

365 76, 36518905, 365203, 36523008, 360 51, G11C 1300

Patent

active

055983642

ABSTRACT:
A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

REFERENCES:
patent: 4811125 (1989-03-01), Sengoku
patent: 4964107 (1990-10-01), Galbraith et al.
patent: 5414390 (1995-05-01), Kovacs et al.
Analog Devices, Inc., 1992, Special Linear Reference Manual, pp. 5-29-5-30.
Corey Peterson et al., A 3-5.5V CMOS 32 Mb/s Fully Integrated Read Channel for Disk-Drives, IEEE 1993 Custom Integrated Circuits Conference Proceedings, pp. 10.2.1-10.2.4.

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