Standby mode circuit design for SRAM standby power reduction
Standby mode SRAM design for power reduction
Standby voltage boosting stage and method for a memory device
State of health monitored flash backed dram module
Static memory cell having independent data holding voltage
Static random access memory device and method of reducing...
Storage device using dynamic RAM
Supply voltage detecting circuit of a semiconductor memory devic
Switch circuit provided with means for setting up the initial co
Synchronous semiconductor memory device for reducing power...
System and method for RAM power and data backup utilizing a capa
System comprising a state-monitoring memory element
Systems, methods and devices for monitoring capacitive...
Systems, methods and devices for power control in mass...