Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2002-07-25
2004-05-18
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Powering
Data preservation
C365S227000, C365S189090, C327S535000, C327S537000
Reexamination Certificate
active
06738305
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a new standby mode circuit design to reduce the power dissipation of static random access memory, SRAM circuitry.
More particularly this invention relates to providing a reduced power supply voltage to SRAM memory cells so as to reduce the power dissipation of memory cells, while utilizing the full power supply voltage for the SRAM bit line and peripheral circuitry so as to preserve memory access performance.
2. Description of Related Art
As semiconductor integrated circuits become more dense and complex, the power consumption requirements are increasing dramatically. In addition, these dense integrated circuits include integrated static random access memory. In many applications, integrated circuits with SRAM must be operated using battery technology. The current available from batteries is limited. Therefore, there is a need to find ways to reduce the power consumption of all integrated circuits, especially memory. As portable, battery-operated circuit functions become more complex, they utilize more and more integrated memory. However, the circuit and memory design must operated at faster speeds. The design of high performance memory with reduced power consumption is an on-going area of invention in today's circuit technology.
U.S. Pat. No. 6,046,627 (ltoh, et al.) “Semiconductor Device Capable of Operating Stably with Reduced Power Consumption” describes a memory circuit device which allows reduced power dissipation via reduced substrate bias voltage, reduced power supply voltage and reduced threshold voltages.
U.S. Pat. No. 6,344,992 B1 (Nakamura) “SRAM Operating with a Reduced Power Dissipation” describes a SRAM design provides for reduced power dissipation by using circuitry which generates different voltage reference levels as a function of SRAM design and mode.
U.S. Pat. No. 6,294,404 (Sato) “Semiconductor Integrated Circuit Having Function of Reducing a Power Consumption and Semiconductor Integrated Circuit System Comprising this Semiconductor Integrated Circuit” discloses an SRAM circuit which creates a standby state which results in power reduction.
U.S. Pat. No. 6,088,269 (Lambertson) “Compact Page-Erasable EEPROM Non-Volatile Memory” discloses a page erasable memory which uses two layers of conductive or semiconductive material.
U.S. Pat. No. 5,541,885 (Takashima) “High Speed Memory with Low Standby Current” discloses a semiconductor memory device which consumes a very small amount of current during standby mode.
BRIEF SUMMARY OF THE INVENTION
It is the objective of this invention to provide a new standby mode circuit design to reduce the power dissipation of static random access memory, SRAM circuitry.
It is further an object of this invention to provide a reduced power supply voltage to SRAM memory cells so as to reduce the power dissipation of memory cells, while utilizing the full power supply voltage for the SRAM bit line and peripheral circuitry so as to preserve memory access performance.
The objects of this invention are achieved by a standby mode circuit for SRAM standby power reduction made up of an input stage whose input is a primary input control signal and whose output drives a mid-stage, a mid stage whose input comes from said input stage and whose output drives an output stage, and an output stage whose input comes from said mid-stage and whose output is the primary output of this standby power reduction circuit and which drives the Vcc node of an SRAM. The standby mode power reduction circuit contains two devices, a p-channel metal oxide semiconductor field effect transistor PMOS FET and an n-channel metal oxide semiconductor field effect transistor NMOS FET. The standby mode power reduction circuit input stage PMOS FET has its gate connected to a primary input control signal, its source connected to a power supply Vdd and its drain connected to a drain of the NMOS FET in the input stage, and connected to the input of the mid-stage. The standby mode power reduction circuit of the input stage has an NMOS FET which has its source connected to Vss or ground, its gate connected to the primary input control signal and its drain connected to the drain of the PMOS FET of the input stage and connected to the primary input of the mid-stage.
The standby node power reduction circuits mid-stage contains two devices, a p-channel metal oxide semiconductor field effect transistor PMOS FET and an n-channel metal oxide semiconductor field effect transistor NMOS FET. The standby node power reduction circuit's mid-stage PMOS FET has its gate connected to the output node from the input stage, has its source connected to a power supply Vdd and its drain connected to a drain of the NMOS FET in the mid-stage and this mid stage output node connected to the input of the output stage. The standby node power reduction circuit's mid-stage NMOS FET has its gate connected to the output node from the input stage, has its source connected to a power supply Vdd and its drain connected to the drain of the PMOS FET in the mid-stage and this mid-stage output node connected to the input of the output stage.
The standby node power reduction circuit's output stage contains two devices, a PMOS FET and an NMOS FET. The standby node power reduction circuit's output stage PMOS FET has its gate connected to the input stage output node, its source connected to the mid-stage output node and its drain connected to the output stage output node.
The standby node power reduction circuit's output stage NMOS FET has its gate and drain are both connected to the the Vdd power supply voltage, and its source is connected to the output stage output node.
The standby node power reduction circuit has a primary input control signal which selects either active node or standby node. The standby node power reduction circuit has a primary output which provides a lower Vcc node voltage to an SRAM during standby node in order to save power.
The standby node power reduction circuit has a primary output which provides the standard Vdd voltage to the SRAM during active mode and provides PMOS FET of the output stage provides a voltage, Vdd to the primary output node to the SRAM during active node. The standby node power reduction circuit's NMOS FET of the output stage provides a voltage reduced from Vdd by Vt to the SRAM where Vt equals NMOS threshold voltage. The standby node power reduction circuit's primary output provides a low Vcc (Vdd-Vt) where Vt is threshold of MOS FET during standby node, in order for save power dissipation. The standby node power reduction circuit's primary output provides reduced Vcc power for the memory cells during standby but maintain a full Vdd on SRAM periphery circuits and bit lines for field performance. The standby node power reduction circuit's primary output provides a full Vcc voltage level during active node.
REFERENCES:
patent: 5541885 (1996-07-01), Takashima
patent: 5644546 (1997-07-01), Furumochi et al.
patent: 5901103 (1999-05-01), Harris et al.
patent: 6046627 (2000-04-01), Itoh et al.
patent: 6088269 (2000-07-01), Lambertson
patent: 6100563 (2000-08-01), Arimoto
patent: 6294404 (2001-09-01), Sato
patent: 6344992 (2002-02-01), Nakamura
patent: 2001/0028591 (2001-10-01), Yamauchi
Ackerman Stephen B.
Le Toan
Lebentritt Michael S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Standby mode circuit design for SRAM standby power reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Standby mode circuit design for SRAM standby power reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Standby mode circuit design for SRAM standby power reduction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3249934