Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2007-09-19
2011-11-22
Phung, Anh (Department: 2824)
Static information storage and retrieval
Powering
Data preservation
C365S226000, C365S154000
Reexamination Certificate
active
08064281
ABSTRACT:
Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.
REFERENCES:
patent: 5500823 (1996-03-01), Martin et al.
patent: 5530673 (1996-06-01), Tobita et al.
patent: 5708589 (1998-01-01), Beauvais
patent: 5956279 (1999-09-01), Mo et al.
patent: 6101617 (2000-08-01), Burckhartt et al.
patent: 6215352 (2001-04-01), Sudo
patent: 6256754 (2001-07-01), Roohparvar
patent: 6754101 (2004-06-01), Terzioglu et al.
patent: 6853598 (2005-02-01), Chevallier
patent: 6901014 (2005-05-01), Son et al.
patent: 7193901 (2007-03-01), Ruby et al.
patent: 7283410 (2007-10-01), Hsu et al.
patent: 7616509 (2009-11-01), Qureshi et al.
patent: 2007/0091698 (2007-04-01), Watanabe et al.
patent: 2008/0049507 (2008-02-01), Lee
patent: 802631 (1997-10-01), None
Tektronix, Tektronix Logic Analyzers TLA7000 Series Data Sheet, Jun. 23, 2009.
Calhoun et al. “Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures,” IEEE Journal of Solid-State Circuits, vol. 39, No. 9, Sep. 2004 pp. 1504-1511.
Enomoto et al. “A Self-Controllable Voltage Level (SVL) Circuit and its Low-Power High-Speed CMOS Circuit Applications,” IEE Journal of Solid-State Circuits, vol. 38, No. 7, Jul. 2003, pp. 1220-1226.
U.S. Patent and Trademark Office; PCT International Search Report; Sep. 5, 2008; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/865,672 Apr. 20, 2011; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/865,672 Mar. 2, 2011; 8 pages.
USPTO Final Rejection for U.S. Appl. No. 11/865,672 Dec. 30, 2009; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/865,672 Jul. 17, 2009; 6 pages.
U.S. Appl. No. 12/238,893: “Method and System of Digital Signal Processing,” Monte Mar, Filed on Sep. 26, 2008; 26 pages.
U.S. Appl. No. 12/239,450: “Digital Signal Processor Control Architecture,” Monte Mar, Filed on Sep. 26, 2008; 28 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/859,547 dated Oct. 1, 2009; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/967,243 dated Sep. 17, 2009; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/967,240 dated Jun. 10, 2009; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,291 dated Apr. 15, 2010; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,291 dated Jan. 13, 2010; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,291 dated Oct. 5, 2009; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,291 dated Sep. 21, 2009; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,291 dated May 5, 2009; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/965,291 dated Dec. 17, 2008; 8 pages.
U.S. Appl. No. 13/099,334: “Univerasal digital Block Interconnection and Channel Routing”, Warren Snyder et al., Filed on May 2, 2011; 31 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/786,412 dated Jan. 31, 2011; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated May 12, 2011; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated Jan. 6, 2011; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated Sep. 15, 2010; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated May 19, 2010; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated Feb. 12, 2010; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated Nov. 2, 2009; 4 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/965,677 dated Sep. 10, 2009; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/965,677 dated Mar. 10, 2009; 10 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/968,145 dated Jan. 5, 2011; 8 pages.
USPTO Final Rejection for U.S. Appl. No. 11/968,145 dated Aug. 2, 2010; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/968,145 dated Mar. 4, 2010; 11 pages.
U.S. Appl. No. 12/104,391: “Clock Driven Dynamic Datapath Chaining,” Warren Synder et al., Filed on Apr. 16, 2008; 31 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/060,176 dated Apr. 6, 2011; 23 pages.
USPTO Final Rejection for U.S. Appl. No. 12/060,176 dated Oct. 12, 2010; 22 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/060,176 dated Mar. 30, 2010; 22 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/104,672 dated Jun. 2, 2011; 9 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/104,672 dated Feb. 14, 2011; 9 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/104,672 dated Oct. 28, 2010; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/104,672 dated Jul. 22, 2010; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/104,672 dated Apr. 19, 2010; 8 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/104,672 dated Jan. 11, 2010; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/104,672 dated Aug. 26, 2009; 11 pages.
USPTO Advisory Action for U.S. Appl. No. 12/104,678 dated Feb. 16, 2011; 5 pages.
USPTO Final Rejection for U.S. Appl. No. 12/104,678 dated Dec. 3, 2010; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/104,678 dated Jul. 2, 2010; 8 pages.
USPTO Final Rejection for U.S. Appl. No. 11/963,661 dated May 6, 2011; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/963,661 dated Dec. 3, 2010; 18 pages.
USPTO Advisory Action for U.S. Appl. No. 11/963,661 dated Aug. 27, 2010; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 11/963,661 dated Jun. 22, 2010; 11 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/963,661 dated Feb. 4, 2010; 11 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/060,128 dated Oct. 19, 2009; 8 pages.
USPTO Non-final Rejection for U.S. Appl. No. 12/060,128 dated Apr. 29, 2009; 11 pages.
Sheets Michael
Williams Timothy
Cypress Semiconductor Corporation
Phung Anh
Reidlinger R Lance
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