Standby mode SRAM design for power reduction

Details Standby mode SRAM design for power reduction Standby mode SRAM design for power reduction

2006-08-15

2006-08-15

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S227000, C365S189090

Reexamination Certificate

active

07092309

ABSTRACT:
A method and system is disclosed for controlling power supply to a memory device. After determining at least one word line being selected, supply voltage lines are controlled so that a predetermined active mode voltage is provided to one or more predetermined memory cells associated with the selected word line, and a standby voltage lower than the active mode voltage is provided to all other unselected portions of the memory device.

REFERENCES:
patent: 6046627 (2000-04-01), Itoh et al.
patent: 6067256 (2000-05-01), Yamashita et al.
patent: 6212124 (2001-04-01), Noda
patent: 6294404 (2001-09-01), Sato
patent: 6683805 (2004-01-01), Joshi et al.
patent: 6738305 (2004-05-01), Liaw
patent: 2004/0252573 (2004-12-01), Hanson et al.

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